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NJU6678V NJU6678V preliminary preliminary 104-common x 132-segment 104-common x 132-segment bit map lcd driver bit map lcd driver package outline package outline NJU6678Vcl NJU6678Vcl general description general description features features the the NJU6678V NJU6678V is a 104-common x 132-segment bit map lcd driver to is a 104-common x 132-segment bit map lcd driver to display graphics or characters. display graphics or characters. it contains 21,120 bits display data ram, microprocessor interface cir- it contains 21,120 bits display data ram, microprocessor interface cir- cuits, instruction decoder, and common and segment drivers. cuits, instruction decoder, and common and segment drivers. an image data from cpu through the serial or 8-bit parallel interface are an image data from cpu through the serial or 8-bit parallel interface are stored into the 21,120 bits internal display data ram and are displayed stored into the 21,120 bits internal display data ram and are displayed on the lcd panel through the commons and segments drivers. on the lcd panel through the commons and segments drivers. the the NJU6678V NJU6678V displays 104 x 132 dots graphics or 8-character 6-line displays 104 x 132 dots graphics or 8-character 6-line by 16 x 16 dots character. by 16 x 16 dots character. the the NJU6678V NJU6678V contains a built-in osc circuit for reducing external com- contains a built-in osc circuit for reducing external com- ponents. and it features partial display function containing selectable ponents. and it features partial display function containing selectable active display block(s) (two blocks max.) and optimizing the duty cycle active display block(s) (two blocks max.) and optimizing the duty cycle ratio. this function dramatically reduces the operating current, setting ratio. this function dramatically reduces the operating current, setting the optimum boosted voltage combined with a programmable voltage the optimum boosted voltage combined with a programmable voltage booster circuit and an electrical variable resister. as result, it reduces booster circuit and an electrical variable resister. as result, it reduces the operating current. the operating current. the operating voltage from 2.5v to 3.3v and low operating current are the operating voltage from 2.5v to 3.3v and low operating current are suitable for small size battery operation items. suitable for small size battery operation items. direct correspondence of display data ram to lcd pixel direct correspondence of display data ram to lcd pixel display data ram - 21,120 bits ;(1.5 times over than display size) display data ram - 21,120 bits ;(1.5 times over than display size) lcd drivers - 104-common and 132-segment lcd drivers - 104-common and 132-segment direct connection to 8-bit microprocessor interface for both of 68 and 80 type mpu direct connection to 8-bit microprocessor interface for both of 68 and 80 type mpu serial interface serial interface partial display function two limited active display blocks setting. duty ratio set automatically. partial display function two limited active display blocks setting. duty ratio set automatically. . . easy vertical scroll by setting the start line address of over size display data ram easy vertical scroll by setting the start line address of over size display data ram programmable bias selection ; 1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11 bias programmable bias selection ; 1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11 bias common driver order assignment by mask option common driver order assignment by mask option version version c c 0 0 to c to c 103 103 (pin name) (pin name) NJU6678Va NJU6678Va com com 0 0 to com to com 103 103 NJU6678Vb NJU6678Vb com com 103 103 to com to com 0 0 useful instruction sets useful instruction sets display on/off cont, display start line set, page address set, column address set, status read, display on/off cont, display start line set, page address set, column address set, status read, display data read/write, inverse display, all on/off, partial display, bias select, n-line inverse, display data read/write, inverse display, all on/off, partial display, bias select, n-line inverse, voltage booster circuits multiple select(maximum 5-time), read modify write, power saving, adc select, etc. voltage booster circuits multiple select(maximum 5-time), read modify write, power saving, adc select, etc. power supply circuits for lcd; programmable voltage booster circuits(5-time maximum, power supply circuits for lcd; programmable voltage booster circuits(5-time maximum, voltage boosting voltage boosting polarity:negative voltage(v polarity:negative voltage(v dd dd common) common) ),regulator, voltage follower (x 4) ),regulator, voltage follower (x 4) precision electrical variable resistance precision electrical variable resistance low power consumption low power consumption operating voltage operating voltage --- 2.5v to 3.3v --- 2.5v to 3.3v lcd driving voltage lcd driving voltage --- 6.0v to 17v --- 6.0v to 17v package outline package outline --- cof / tcp / bumped chip --- cof / tcp / bumped chip c-mos technology ( c-mos technology ( substrate:n) substrate:n) 2001 2001 ver.4.8 ver.4.8
NJU6678V NJU6678V pad location pad location chip center chip center : x=0um,y=0um : x=0um,y=0um chip size chip size : x=5.36mm,y=5.31mm : x=5.36mm,y=5.31mm chip thickness chip thickness : 675um : 675um + + 30um 30um bump size bump size : 45um x 83um : 45um x 83um pad pitch pad pitch : 60um(min) : 60um(min) bump height bump height : 15um typ. : 15um typ. bump material bump material : au : au voltage boosting polarity voltage boosting polarity :negative voltage (vdd common) :negative voltage (vdd common) substrate substrate :n :n c 1 - t 1 t 2 a 0 c s v 5 v r v o u t c 2 - c 2 + c 1 + c e l 6 8 p / s v s s v d d v s s d 7 ( s i ) d 6 ( s c l ) d 5 d 4 d 3 d 2 d 0 d 1 r d w r s 2 8 s 2 9 s 1 0 3 s 1 0 2 s 1 0 4 s 1 0 5 s 1 3 0 s 1 3 1 c 1 0 3 c 1 0 2 c 5 3 s 2 7 s 2 6 s 1 s 0 c 5 1 c 5 0 c 1 c 0 v 1 v d d r e s c 5 2 y x c 3 - c 4 - c 4 + c 3 + o s c 2 o s c 1 d u m m y 3 d u m m y 5 d u m m y 6 d u m m y 7 d u m m y 0 d u m m y 1 d u m m y 2 d u m m y 4 v 4 v 2 v 3
NJU6678V NJU6678V pad no. terminal x= um y= um pad no. terminal x= um y= um 1 dummy0 -2250 -2497 51 c 4 2523 -2130 2 dummy1 -2190 -2497 52 c 5 2523 -2070 3 dummy2 -2130 -2497 53 c 6 2523 -2010 4 dummy3 -2070 -2497 54 c 7 2523 -1950 5 dummy4 -2010 -2497 55 c 8 2523 -1890 6 dummy5 -1950 -2497 56 c 9 2523 -1830 7 dummy6 -1890 -2497 57 c 10 2523 -1770 8 dummy7 -1830 -2497 58 c 11 2523 -1710 9 v dd -1747 -2497 59 c 12 2523 -1650 10 p/s -1666 -2497 60 c 13 2523 -1590 11 sel68 -1596 -2497 61 c 14 2523 -1530 12 res -1487 -2497 62 c 15 2523 -1470 13 v ss -1417 -2497 63 c 16 2523 -1410 14 t 2 -1347 -2497 64 c 17 2523 -1350 15 t 1 -1238 -2497 65 c 18 2523 -1290 16 osc 1 -1168 -2497 66 c 19 2523 -1230 17 osc 2 -1049 -2497 67 c 20 2523 -1170 18 cs -979 -2497 68 c 21 2523 -1110 19 a0 -861 -2497 69 c 22 2523 -1050 20 wr -791 -2497 70 c 23 2523 -990 21 rd -667 -2497 71 c 24 2523 -930 22 d 0 -510 -2497 72 c 25 2523 -870 23 d 1 -289 -2497 73 c 26 2523 -810 24 d 2 -69 -2497 74 c 27 2523 -750 25 d 3 152 -2497 75 c 28 2523 -690 26 d 4 372 -2497 76 c 29 2523 -630 27 d 5 592 -2497 77 c 30 2523 -570 28 d 6(scl) 813 -2497 78 c 31 2523 -510 29 d 7(si) 1033 -2497 79 c 32 2523 -450 30 v ss 1191 -2497 80 c 33 2523 -390 31 v out 1261 -2497 81 c 34 2523 -330 32 c4 + 1331 -2497 82 c 35 2523 -270 33 c4 - 1401 -2497 83 c 36 2523 -210 34 c3 + 1471 -2497 84 c 37 2523 -150 35 c3 - 1541 -2497 85 c 38 2523 -90 36 c2 + 1611 -2497 86 c 39 2523 -30 37 c2 - 1681 -2497 87 c 40 2523 30 38 c1 + 1751 -2497 88 c 41 2523 90 39 c1 - 1821 -2497 89 c 42 2523 150 40 vr 1891 -2497 90 c 43 2523 210 41 v 5 1961 -2497 91 c 44 2523 270 42 v 4 2031 -2497 92 c 45 2523 330 43 v 3 2101 -2497 93 c 46 2523 390 44 v 2 2171 -2497 94 c 47 2523 450 45 v 1 2241 -2497 95 c 48 2523 510 46 v dd 2311 -2497 96 c 49 2523 570 47 c 0 2523 -2370 97 c 50 2523 630 48 c 1 2523 -2310 98 c 51 2523 690 49 c 2 2523 -2250 99 s 0 2523 750 50 c 3 2523 -2190 100 s 1 2523 810 terminal description terminal description chip size 5.36 x 5.31mm (chip center x=0um,y=0um) chip size 5.36 x 5.31mm (chip center x=0um,y=0um)
NJU6678V NJU6678V pad no. terminal x= um y= um pad no. terminal x= um y= um 101 s 2 2523 870 151 s 52 810 2497 102 s 3 2523 930 152 s 53 750 2497 103 s 4 2523 990 153 s 54 690 2497 104 s 5 2523 1050 154 s 55 630 2497 105 s 6 2523 1110 155 s 56 570 2497 106 s 7 2523 1170 156 s 57 510 2497 107 s 8 2523 1230 157 s 58 450 2497 108 s 9 2523 1290 158 s 59 390 2497 109 s 10 2523 1350 159 s 60 330 2497 110 s 11 2523 1410 160 s 61 270 2497 111 s 12 2523 1470 161 s 62 210 2497 112 s 13 2523 1530 162 s 63 150 2497 113 s 14 2523 1590 163 s 64 90 2497 114 s 15 2523 1650 164 s 65 30 2497 115 s 16 2523 1710 165 s 66 -30 2497 116 s 17 2523 1770 166 s 67 -90 2497 117 s 18 2523 1830 167 s 68 -150 2497 118 s 19 2523 1890 168 s 69 -210 2497 119 s 20 2523 1950 169 s 70 -270 2497 120 s 21 2523 2010 170 s 71 -330 2497 121 s 22 2523 2070 171 s 72 -390 2497 122 s 23 2523 2130 172 s 73 -450 2497 123 s 24 2523 2190 173 s 74 -510 2497 124 s 25 2523 2250 174 s 75 -570 2497 125 s 26 2523 2310 175 s 76 -630 2497 126 s 27 2523 2370 176 s 77 -690 2497 127 s 28 2250 2497 177 s 78 -750 2497 128 s 29 2190 2497 178 s 79 -810 2497 129 s 30 2130 2497 179 s 80 -870 2497 130 s 31 2070 2497 180 s 81 -930 2497 131 s 32 2010 2497 181 s 82 -990 2497 132 s 33 1950 2497 182 s 83 -1050 2497 133 s 34 1890 2497 183 s 84 -1110 2497 134 s 35 1830 2497 184 s 85 -1170 2497 135 s 36 1770 2497 185 s 86 -1230 2497 136 s 37 1710 2497 186 s 87 -1290 2497 137 s 38 1650 2497 187 s 88 -1350 2497 138 s 39 1590 2497 188 s 89 -1410 2497 139 s 40 1530 2497 189 s 90 -1470 2497 140 s 41 1470 2497 190 s 91 -1530 2497 141 s 42 1410 2497 191 s 92 -1590 2497 142 s 43 1350 2497 192 s 93 -1650 2497 143 s 44 1290 2497 193 s 94 -1710 2497 144 s 45 1230 2497 194 s 95 -1770 2497 145 s 46 1170 2497 195 s 96 -1830 2497 146 s 47 1110 2497 196 s 97 -1890 2497 147 s 48 1050 2497 197 s 98 -1950 2497 148 s 49 990 2497 198 s 99 -2010 2497 149 s 50 930 2497 199 s 100 -2070 2497 150 s 51 870 2497 200 s 101 -2130 2497
NJU6678V NJU6678V pad no. terminal x= um y= um pad no. terminal x= um y= um 201 s 102 -2190 2497 251 c 83 -2524 -510 202 s 103 -2250 2497 252 c 82 -2524 -570 203 s 104 -2524 2370 253 c 81 -2524 -630 204 s 105 -2524 2310 254 c 80 -2524 -690 205 s 106 -2524 2250 255 c 79 -2524 -750 206 s 107 -2524 2190 256 c 78 -2524 -810 207 s 108 -2524 2130 257 c 77 -2524 -870 208 s 109 -2524 2070 258 c 76 -2524 -930 209 s 110 -2524 2010 259 c 75 -2524 -990 210 s 111 -2524 1950 260 c 74 -2524 -1050 211 s 112 -2524 1890 261 c 73 -2524 -1110 212 s 113 -2524 1830 262 c 72 -2524 -1170 213 s 114 -2524 1770 263 c 71 -2524 -1230 214 s 115 -2524 1710 264 c 70 -2524 -1290 215 s 116 -2524 1650 265 c 69 -2524 -1350 216 s 117 -2524 1590 266 c 68 -2524 -1410 217 s 118 -2524 1530 267 c 67 -2524 -1470 218 s 119 -2524 1470 268 c 66 -2524 -1530 219 s 120 -2524 1410 269 c 65 -2524 -1590 220 s 121 -2524 1350 270 c 64 -2524 -1650 221 s 122 -2524 1290 271 c 63 -2524 -1710 222 s 123 -2524 1230 272 c 62 -2524 -1770 223 s 124 -2524 1170 273 c 61 -2524 -1830 224 s 125 -2524 1110 274 c 60 -2524 -1890 225 s 126 -2524 1050 275 c 59 -2524 -1950 226 s 127 -2524 990 276 c 58 -2524 -2010 227 s 128 -2524 930 277 c 57 -2524 -2070 228 s 129 -2524 870 278 c 56 -2524 -2130 229 s 130 -2524 810 279 c 55 -2524 -2190 230 s 131 -2524 750 280 c 54 -2524 -2250 231 c 103 -2524 690 281 c 53 -2524 -2310 232 c 102 -2524 630 282 c 52 -2524 -2370 233 c 101 -2524 570 234 c 100 -2524 510 235 c 99 -2524 450 236 c 98 -2524 390 237 c 97 -2524 330 238 c 96 -2524 270 239 c 95 -2524 210 240 c 94 -2524 150 241 c 93 -2524 90 242 c 92 -2524 30 243 c 91 -2524 -30 244 c 90 -2524 -90 245 c 89 -2524 -150 246 c 88 -2524 -210 247 c 87 -2524 -270 248 c 86 -2524 -330 249 c 85 -2524 -390 250 c 84 -2524 -450
NJU6678V NJU6678V block diagram block diagram c 0 c 5 1 s 0 s 1 3 1 c 1 0 3 c 5 2 v s s v d d v 1 t o v 5 v r t 1 , t 2 1 6 0 x 1 3 2 c s a 0 r d w r s e l 6 8 p / s r e s o s c 1 d 0 t o d 7 ( s i , s c l ) 5 c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - o s c 2 c o m d r i v e r s e g d r i v e r c o m d r i v e r s h i f t r e g i s t e r d i s p l a y d a t a l a t c h v o l t a g e g e n e r a t o r r o w a d d r e s s d e c o d e r o u t p u t a s s i g n m e n t r e g i s t e r p a g e a d d r e s s r e g i s t e r i / o b u f f e r i n s t r u c t i o n d e c o d e r r e s e t s t a t u s c u l u m n a d d r e s s r e g i s t e r c u l u m n a d d r e s s c o u n t e r m u l t i p l e x e r b f d i s p l a y t i m i n g g e n e r a t o r b u s h o l d e r o s c . l i n e a d d r e s s d e c o d e r l i n e c o u n t e r s h i f t r e g i s t e r c o m s e g g e n e r a t o r t i m i n g m p u i n t e r f a c e i n t e r n a l b u s d i s p l a y d a t a r a m c u l u m n a d d r e s s d e c o d e r s t a r t l i n e r e g i s t e r
NJU6678V NJU6678V no. symbol i/o f u n c t i o n 1 to 8 dummy0 to dummy7 dummy terminals. these are open terminals electrically. 9,46 v dd power power supply terminal (+2.5v - +3.3v) 13,30 v ss gnd ground terminal (0v) 45 44 43 42 41 v 1 v 2 v 3 v 4 v 5 power lcd driving voltage supplying terminals. i n case of the external power supply operation without internal power supply operation, each level of lcd driving voltage is supplied from outside fitting with following relation. v dd > v1 > v2 > v3 > v4 > v5 > v out in case of the internal power supply, lcd driving voltages v1-v4 depending on the bias selection are supplied as shown in follows; (v lcd =v dd -v 5 ) 38,39 36,37 34,35 32,33 c1 + ,c1 - c2 + ,c2 - c3 + ,c3 - c4 + ,c4 - o capacitor connecting terminals for internal voltage booster.boosting time is programmed by instruction (2 to 5 times ) 31 v out o boost ed voltage output terminal. connects the capacitor between v out terminal and v ss . 40 vr i v lcd voltage adjustment terminal. the gain of v lcd setup circuit for v5 level is adjusted by external resistors. 15 14 t 1 t 2 i lcd bias voltage control terminals. 22 to 29 d 0 to d 7 (si) (scl) i/o data input/output terminals. in pararel interface mode (p/s="h") i/o terminals of 8-bit bus. in serial interface mode (p/s="l") d 7 : input terminal of serial data ( si ). d 6 : input terminal of serial data clock ( scl ). d 0 to d 5 terminals are hi-impedance. when cs="h", d 0 to d 7 terminals are hi-impedance. 19 a0 i data discremination signal input terminal. the signal from mpu discreminates transmoitted data between display data and instruction. 12 res i reset terminal. reset operation is executing during "l" state of res. 18 cs i chip select signal input terminal. data input/output are available during cs ="l". terminal description terminal description bias v 1 v 2 v 3 v 4 1/4 bias v 5 +3/4v lcd v 5 +2/4v lcd v 5 +2/4v lcd v 5 +1/4v lcd 1/5 bias v 5 +4/5v lcd v 5 +3/5v lcd v 5 +2/5v lcd v 5 +1/5v lcd 1/6 bias v 5 +5/6v lcd v 5 +4/6v lcd v 5 +2/6v lcd v 5 +1/6v lcd 1/7 bias v 5 +6/7v lcd v 5 +5/7v lcd v 5 +2/7v lcd v 5 +1/7v lcd 1/8 bias v 5 +7/8v lcd v 5 +6/8v lcd v 5 +2/8v lcd v 5 +1/8v lcd 1/9 bias v 5 +8/9v lcd v 5 +7/9v lcd v 5 +2/9v lcd v 5 +1/9v lcd 1/10 bias v 5 +9/10v lcd v 5 +8/10v lcd v 5 +2/10v lcd v 5 +1/10v lcd 1/11 bias v 5 +10/11v lcd v 5 +9/11v lcd v 5 +2/11v lcd v 5 +1/11v lcd t 1 t 2 voltage booster cir. voltage adj. v/f cir. l l/h available available available h l not avail. available available h h not avail. not avail. available a0 h l distin. display data instruction
NJU6678V NJU6678V no symbol i/o f u n c t i o n 21 rd(e) i rd(80 type) or e(68 type) signal input terminal. ( sel68="l" ) rd signal from 80 type mpu input terminal. active "l". d 0 to d 7 terminals are output during "l" level. ( sel68="h" ) enable signal from 68 type mpu input terminal. active "h". 20 wr(rw) i wr(80 type) or r/w(68 type) signal input terminal ( sel68="l" ) wr signal from 80 type mpu input terminal. active "l". the data transmitted during wr="l" are fetched at the rising edge of wr. ( sel68="h" ) r/w signal from 68 type mpu input terminal. 11 sel68 i mpu interface type selection terminal. this terminal must connect to v dd or v ss . 10 p/s i parallel or serial interface selection signal input terminal. in case of serial interface( p/s="l") ram data and status read operation do not work in mode of the serial interface. rd and wr terminals must fix to "h" or "l". d 0 to d 5 terminals are hi-impedance. 16 17 osc 1 osc 2 i external clock input terminal. in internal oscillation operation, osc1 and osc2 terminals should be open.in external clock operation, the external clock input to osc1 terminal. 47 to 98 c 0 to c 51 o lcd driving signal output terminals. common output terminals:c 0 to c 103 segment output terminals:s 0 to s 131 common output terminal following output voltage is selected by the combination of alternating (fr) signal and common scanning data. segment output terminal following output voltage is selected by the combination of alternating (fr) signal and display data in the dd ram. 99 to 230 s 0 to s 131 o 282 to 231 c 52 to c 103 o sel68 h l state 68 type 80 type p/s chip select data/command data read/write serial clock "h" cs a d 0 to d 7 rd,wr - "l" cs a0 si(d 7 ) - scl(d 6 ) scan data fr output voltage h h v 5 l v dd l h v 1 l v 4 ram data fr output voltage normal reverse h h v dd v 2 l v 5 v 3 l h v 2 v dd l v 3 v 5 r/w h l state read write
NJU6678V NJU6678V (1) description for each blocks (1) description for each blocks (1-2)display start line register (1-2)display start line register the display start line register is a register to set a display data ram address corresponding to the com the display start line register is a register to set a display data ram address corresponding to the com 0 0 display line (the top line normally) for the vertical scroll on the lcd, page address change and so forth. the display line (the top line normally) for the vertical scroll on the lcd, page address change and so forth. the display start line address set instruction sets the 8-bit display start address into this register. display start line address set instruction sets the 8-bit display start address into this register. functional description functional description (1-1) busy flag (bf) (1-1) busy flag (bf) the busy flag (bf) is set to logical ?1? in busy of internal execution by an instruction, and any instruction the busy flag (bf) is set to logical ?1? in busy of internal execution by an instruction, and any instruction excepting for the ?status read? is disable at this time. busy flag is outputted through d excepting for the ?status read? is disable at this time. busy flag is outputted through d 7 7 terminal by ?status terminal by ?status read? instruction. although another instructions should be inputted after check of busy flag, no need to check read? instruction. although another instructions should be inputted after check of busy flag, no need to check busy flag if the system cycle time (t busy flag if the system cycle time (t cyc cyc ) as shown in ) as shown in ac characteristics is secured completely. ac characteristics is secured completely. . . (1-3) line counter (1-3) line counter line counter is reset when the internal fr signal is switched and outputs the line address of the display data line counter is reset when the internal fr signal is switched and outputs the line address of the display data ram by count up operation synchronizing with common cycle of ram by count up operation synchronizing with common cycle of NJU6678V NJU6678V . . (1-4) column address counter (1-4) column address counter column address counter is the 8-bit preset-able counter to point the column address of the display data ram column address counter is the 8-bit preset-able counter to point the column address of the display data ram (dd ram) as shown in figure 1. the counter is incremented automatically after the display data read/write (dd ram) as shown in figure 1. the counter is incremented automatically after the display data read/write instructions execution. when the column address counter reaches to the maximum existing address by the instructions execution. when the column address counter reaches to the maximum existing address by the increment operations, the count up operation (increment) is frozen. however, when new address is set to the increment operations, the count up operation (increment) is frozen. however, when new address is set to the column address counter again, it restarts the count up operation from a set address. the operation of column column address counter again, it restarts the count up operation from a set address. the operation of column address counter is independent against page address register. address counter is independent against page address register. by the address inverse instruction (adc select) as shown in figure 1, column address decoder reverses the by the address inverse instruction (adc select) as shown in figure 1, column address decoder reverses the correspondence between column address and segment output of display data ram. correspondence between column address and segment output of display data ram. (1-5) page address register (1-5) page address register page page address register assigns the page address of the display data ram as shown in figure 1. in case of address register assigns the page address of the display data ram as shown in figure 1. in case of accessing from the mpu with changing the page address, page address set instruction is required. accessing from the mpu with changing the page address, page address set instruction is required. ( ( 1-6) display data ram 1-6) display data ram the display data ram (dd ram) is the bit map ram consisting of 21,120 bits to store the display data corre- the display data ram (dd ram) is the bit map ram consisting of 21,120 bits to store the display data corre- sponding to the lcd pixel on lcd panel. sponding to the lcd pixel on lcd panel. the dd ram data and the state of the lcd: the dd ram data and the state of the lcd: in normal display : ?1?=turn-on display, ?0? =turn-off display in normal display : ?1?=turn-on display, ?0? =turn-off display in reveres display : ?1?=turn-off display, ?0? =turn-on display in reveres display : ?1?=turn-off display, ?0? =turn-on display dd ram output 132 bits parallel data addressed by line address counter then the data latched in the display data dd ram output 132 bits parallel data addressed by line address counter then the data latched in the display data latch. asynchronous data access to the dd ram is available due to the access to the dd ram from the cpu latch. asynchronous data access to the dd ram is available due to the access to the dd ram from the cpu and latch to the display data latch operation are done independently. and latch to the display data latch operation are done independently. (1-7) common driver assignment (1-7) common driver assignment this circuit determines the scanning direction this circuit determines the scanning direction of the common output. of the common output. table 1 table 1 com outputs terminals pad no. 47 98 231 282 pin name c 0 c 51 c 103 c 52 ver.a com 0 com 51 com 103 com 52 ver.b com 103 com 52 com 0 com 51 the mask fixes the common scanning direction between version a and b that can not be changed by the instruction. the mask fixes the common scanning direction between version a and b that can not be changed by the instruction.
NJU6678V NJU6678V fig.1 correspondence with display data ram address fig.1 correspondence with display data ram address page address data display pattern line address for example the display start line is 10 h d4,d3,d2,d1,d0 (0,0,0,0,0) d0 pege 0 00 d1 01 d2 02 d3 03 d4 04 d5 05 d6 06 d7 07 d4,d3,d2,d1,d0 (0,0,0,0,1) d0 pege 1 08 d1 09 d2 0a d3 0b d4 0c d5 0d d6 0e d7 0f cn out d4,d3,d2,d1,d0 (0,0,0,1,0) d0 pege 2 10 c0 d1 11 c1 d2 12 c2 d3 13 c3 d4 14 c4 d5 15 c5 d6 16 c6 d7 17 c7 : : : : d0 : : : : 18 c8 d1 19 c9 : : : : : : : : : : : : d6 6e c94 d7 6f c65 d4,d3,d2,d1,d0 (0,1,1,1,0) d0 pege 14 70 c96 d1 71 c97 d2 72 c98 d3 73 c99 d4 74 c100 d5 75 c101 d6 76 c102 d7 77 c103 d4,d3,d2,d1,d0 (0,1,1,1,1) d0 pege 15 78 d1 79 d2 7a d3 7b d4 7c d5 7d d6 7e d7 7f : : : : d0 : : : : 80 d1 81 : : : : : : : : d6 96 d7 97 d4,d3,d2,d1,d0 (1,0,0,1,1) d0 pege 19 98 d1 99 d2 9a d3 9b d4 9c d5 9d d6 9e d7 9f | | | | | | | | | | | | | | | | | | | | column address a d c d 0 ="0" 00 01 02 03 04 05 06 07 08 09 7a 7b 7c 7d 7e 7f 80 81 82 83 d 0 ="1" 83 82 81 80 7f 7e 7d 7c 7b 7a 09 08 07 06 05 04 03 02 01 00 segment output 0 1 2 3 4 5 6 7 8 9 122 123 124 125 126 127 128 129 130 131
NJU6678V NJU6678V (1-8) reset circuit (1-8) reset circuit when the input signal to res terminal goes to ?l?, the reset circuit executes initialization as below; when the input signal to res terminal goes to ?l?, the reset circuit executes initialization as below; the initialization state (default) the initialization state (default) 1 1 display off display off 2 2 normal display (not inverse) normal display (not inverse) 3 3 adc select : normal (adc instruction d adc select : normal (adc instruction d 0 0 =?0?) =?0?) 4 4 read modify write mode off read modify write mode off 5 5 voltage booster off, voltage regulator off, voltage follower off voltage booster off, voltage regulator off, voltage follower off 6 6 static drive off static drive off 7 7 driver output off driver output off 8 8 clear the data of serial interface register clear the data of serial interface register 9 9 set the column address counter to 00 set the column address counter to 00 h h 10 10 set the display start line register to 00 set the display start line register to 00 h h 11 11 set the page address register to page ?0? set the page address register to page ?0? 12 12 set the evr register to ff set the evr register to ff h h 13 13 set the partial display(1/104 duty) set the partial display(1/104 duty) 14 14 set the bias select(1/11 bias) set the bias select(1/11 bias) 15 15 set the voltage booster(5 times) set the voltage booster(5 times) 16 16 set the n-line inverse register to 0 set the n-line inverse register to 0 h h the res terminal connects to the reset terminal of the mpu synchronization with the mpu initialization as shown the res terminal connects to the reset terminal of the mpu synchronization with the mpu initialization as shown in ? the mpu interface ? in the application circuit section. the ?l? level input signal as reset signal must keep the in ? the mpu interface ? in the application circuit section. the ?l? level input signal as reset signal must keep the period over than 10us as shown in dc characteristics. the period over than 10us as shown in dc characteristics. the NJU6678V NJU6678V takes 1us for the reset operation after the takes 1us for the reset operation after the rising edge of the res signal. rising edge of the res signal. the reset operation by res =?l? initializes each resister setting as above reset status, but the internal oscillation the reset operation by res =?l? initializes each resister setting as above reset status, but the internal oscillation circuit and output terminals (d0 to d7) are not affected. circuit and output terminals (d0 to d7) are not affected. to avoid the lock-up, the reset operation by the res terminal must be required every time when power terns on. to avoid the lock-up, the reset operation by the res terminal must be required every time when power terns on. the reset operation by the reset instruction, function 9 to 16 operations mentioned above is performed. the reset operation by the reset instruction, function 9 to 16 operations mentioned above is performed. the res terminal must be keep ?l? level when the power terns on in not use of the built-in lcd power supply circuit the res terminal must be keep ?l? level when the power terns on in not use of the built-in lcd power supply circuit for no affect to the internal execution. for no affect to the internal execution. (1-9) lcd driving circuit (1-9) lcd driving circuit (a) lcd driving circuits (a) lcd driving circuits lcd driver is 236 sets of multiplexer consisting of 132 segments and 104 commons drivers to output lcd driving lcd driver is 236 sets of multiplexer consisting of 132 segments and 104 commons drivers to output lcd driving voltage. the common driver outputs the common scan signals formed with the shift register. the segment driver voltage. the common driver outputs the common scan signals formed with the shift register. the segment driver outputs the segment driving signal determined by a combination of display data in the dd ram, common timing, fr outputs the segment driving signal determined by a combination of display data in the dd ram, common timing, fr signal, and alternating signal for lcd. the output wave forms of segment/common are shown in signal, and alternating signal for lcd. the output wave forms of segment/common are shown in lcd driving lcd driving waveform waveform . . (b) display data latch circuits (b) display data latch circuits display data latch circuit latches the 132-bit display data outputted from the dd ram addressed by the line display data latch circuit latches the 132-bit display data outputted from the dd ram addressed by the line address counter to lcd driver at every common signal cycle temporarily. the original data in the dd ram is not address counter to lcd driver at every common signal cycle temporarily. the original data in the dd ram is not changed because of the normal/reverse display, display on/off, static drive on/off instruction processes only changed because of the normal/reverse display, display on/off, static drive on/off instruction processes only stored data in this display data latch circuit. stored data in this display data latch circuit. (c) signal forming to line counter and display data latch circuit (c) signal forming to line counter and display data latch circuit the count clock to line counter and the latch clock to display data latch circuit are formed using the internal the count clock to line counter and the latch clock to display data latch circuit are formed using the internal display clock (cl). the display data of 132 bits from display data ram pointed by the line address synchroniz- display clock (cl). the display data of 132 bits from display data ram pointed by the line address synchroniz- ing with the internal display clock are latched into the display data latch circuit and are outputted to ing with the internal display clock are latched into the display data latch circuit and are outputted to lcd lcd driving circuits. driving circuits. the display data read out operation from dd ram to the lcd driver circuit is completely independent operation with the display data read out operation from dd ram to the lcd driver circuit is completely independent operation with an access to the display data ram from mpu. an access to the display data ram from mpu. (d) display timing generation circuit (d) display timing generation circuit the display timing generation circuit generates the internal timing of the display system by the master clock and the the display timing generation circuit generates the internal timing of the display system by the master clock and the internal fr signal. as for it, the internal fr signal and the lcd alternating signal generate the wave form of 2-frame internal fr signal. as for it, the internal fr signal and the lcd alternating signal generate the wave form of 2-frame alternating drive wave form or the n-line inverse drive method for the lcd driving circuit. alternating drive wave form or the n-line inverse drive method for the lcd driving circuit.
NJU6678V NJU6678V (e)common timing generator (e)common timing generator the common timing generator generates the common timing signal from the display clock (cl ). the common timing generator generates the common timing signal from the display clock (cl ). -2-frame alternating drive mode -2-frame alternating drive mode fig.2 fig.2 -n-line inverse drive mode (n=7, line inverting register sets to 6) -n-line inverse drive mode (n=7, line inverting register sets to 6) fig.3 fig.3 c l f r c 0 c 1 r a m d a t a s n v d d v 1 v 4 v 5 v d d v 1 v 4 v 5 v d d v 2 v 3 v 5 1 0 3 1 0 4 1 2 3 4 5 6 7 8 1 0 1 1 0 2 1 0 3 1 0 4 1 2 3 4 5 1 0 3 1 0 4 1 2 3 4 5 6 7 8 c l f r c 0 c 1 r a m d a t a s n v d d v 1 v 4 v 5 v d d v 1 v 4 v 5 v d d v 2 v 3 v 5 1 0 1 1 0 2 1 0 3 1 0 4 1 2 3 4 5
NJU6678V NJU6678V t 1 t 2 voltage booster voltage adj. buffer(v/f) ext.pow supply c 1+ ,c 1- to c 4 +,c 4- vr term. l l/h on on on - h l off on on v out open h h off off on v 5 ,v out open open duty 1/8 1/16 1/24 1/32 1/40 1/48,56 1/64,72 1/80,88 1/96,104 divide 1/50 1/25 1/16 1/12 1/10 1/8 1/6 1/5 1/4 -the relation between duty and divide -the relation between duty and divide (f) oscillation circuit (f) oscillation circuit the oscillation circuit is a low power type cr oscillator using an internal resistor and capacitor. the oscillator the oscillation circuit is a low power type cr oscillator using an internal resistor and capacitor. the oscillator output is using for the display timing clock and for the voltage booster circuit. and the display clock(cl) is generated output is using for the display timing clock and for the voltage booster circuit. and the display clock(cl) is generated from this oscillator output frequency by dividing. from this oscillator output frequency by dividing. (g) power supply circuit (g) power supply circuit the internal power supply circuit generates the voltage for driving lcd. it consists of voltage booster circuits (from 2 the internal power supply circuit generates the voltage for driving lcd. it consists of voltage booster circuits (from 2 times to 5 times), voltage regulator circuits, and voltage followers. times to 5 times), voltage regulator circuits, and voltage followers. the operation of internal power supply circuits is controlled by the internal power supply on/off instruction. the operation of internal power supply circuits is controlled by the internal power supply on/off instruction. when the internal power supply off instruction is executed, all of the voltage booster circuits, regulator circuits, when the internal power supply off instruction is executed, all of the voltage booster circuits, regulator circuits, voltage follower circuits are turned off. in this time, the bias voltage of v voltage follower circuits are turned off. in this time, the bias voltage of v 1 1 , v , v 2 2 , v , v 3 3 , v , v 4 4 ,v ,v 5 5 and v and v out out for the lcd for the lcd should be supplied from outside, terminals c1 should be supplied from outside, terminals c1 + + , c1 , c1 - - , c2 , c2 + + , c2 , c2 - - , c3 , c3 + + , c3 , c3 - - , c4 , c4 + + , c4 , c4 - - , and vr should be open. the , and vr should be open. the status of internal power supply is selected by t status of internal power supply is selected by t 1 1 and t and t 2 2 terminal. furthermore the external power supply operates terminal. furthermore the external power supply operates with some of internal power supply function. with some of internal power supply function. when (t when (t 1 1 , t , t 2 2 )=(h, l), c1 )=(h, l), c1 + + , c1 , c1 - - , c2 , c2 + + , c2 , c2 - - ,c3 ,c3 + + , c3 , c3 - - , c4 , c4 + + , c4 , c4 - - terminals for voltage booster circuits are open be- terminals for voltage booster circuits are open be- cause the voltage booster circuits doesn't operate. therefore lcd driving voltage to the v cause the voltage booster circuits doesn't operate. therefore lcd driving voltage to the v out out terminal should be terminal should be supplied from outside. supplied from outside. when (t when (t 1 1 , t , t 2 2 )=(h, h), terminals for voltage booster circuits and vr are open, because the voltage booster circuits )=(h, h), terminals for voltage booster circuits and vr are open, because the voltage booster circuits and voltage adjust circuits do not operate. and voltage adjust circuits do not operate. the internal power supply circuits is designed specially for a small-size lcd like as normal cellular phone size the internal power supply circuits is designed specially for a small-size lcd like as normal cellular phone size lcd panel. when lcd panel. when NJU6678V NJU6678V apply to the large size lcd panel application (large capacitive load), external power apply to the large size lcd panel application (large capacitive load), external power supply is required to keep good display condition.. supply is required to keep good display condition.. to keep good display condition, external component of the capacitors connecting to the v1 to v5 terminals and to keep good display condition, external component of the capacitors connecting to the v1 to v5 terminals and voltage booster circuits and the feedback resistors for the v5 operational amplifier must fix each optimized con- voltage booster circuits and the feedback resistors for the v5 operational amplifier must fix each optimized con- stant after checking various display patterns on lcd panel actually in the application. stant after checking various display patterns on lcd panel actually in the application. table 2 table 2 table 3 table 3
NJU6678V NJU6678V power supply applications power supply applications (4) external power supply example (4) external power supply example a a ll of v1 to v5 and v ll of v1 to v5 and v out out supply from outside supply from outside internal power supply (instruction) (t1,t2) =(h,h) internal power supply (instruction) (t1,t2) =(h,h) (1) internal power supply example. (1) internal power supply example. all of the internal booster, voltage regulator, all of the internal booster, voltage regulator, voltage follower using. voltage follower using. internal power supply on (instruction) (t1,t2)=(l,l) internal power supply on (instruction) (t1,t2)=(l,l) (2) only v (2) only v out out supply from outside example. supply from outside example. internal voltage regulator, voltage follower using internal voltage regulator, voltage follower using internal power supply on (instruction) (t1,t2) = (h,l) internal power supply on (instruction) (t1,t2) = (h,l) (3) v (3) v out out and v5 supply from outside example. and v5 supply from outside example. internal voltage follower using. internal voltage follower using. internal power supply (instruction) (t1,t2) =(h,h) internal power supply (instruction) (t1,t2) =(h,h) : these switches should be open during the power save mode. : these switches should be open during the power save mode. + + + + v d d v 1 v 2 v 3 v 4 v 5 v o u t v s s + t 1 t 2 v d d v r v 5 v d d v 1 v 2 v 3 v 4 v 5 v o u t v s s t 1 t 2 + + + + + + v d d v 1 v 2 v 3 v 4 v 5 v o u t v s s t 1 t 2 c 1 + + + + + c 4 + c 3 + c 2 - c 2 + c 1 - c 4 - c 3 - v d d v r v 5 + + + + v d d v 1 v 2 v 3 v 4 v 5 v o u t v s s t 1 t 2
NJU6678V NJU6678V the the NJU6678V NJU6678V distinguishes the data on the data bus d0 to d7 as an instruction by combination of a0, rd, and wr(r/ distinguishes the data on the data bus d0 to d7 as an instruction by combination of a0, rd, and wr(r/ w) signals. the decoding of the instruction and exection performes with only high speed internal timing without relation w) signals. the decoding of the instruction and exection performes with only high speed internal timing without relation to the external clock. therefore, no busy flag check required normally. in case of the serial interface, the data input as to the external clock. therefore, no busy flag check required normally. in case of the serial interface, the data input as msb(d7) first serially. table.4 shows the instruction codes of the msb(d7) first serially. table.4 shows the instruction codes of the NJU6678V NJU6678V . . instruction code description a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 (a) display on/off 0 1 0 1 0 1 0 1 1 1 0/1 lcd display on/off 0:off 1:on (b) display start line set high order 4bits 0 1 0 0 1 0 1 high order address determine the display line of ram to the com0. (set the higher order 4bits) display start line set lower order 4bits 0 1 0 0 1 1 0 lower order address determine the display line of ram to the com0. (set the lower order 4bits) (c) page address set high order 1bits 0 1 0 0 1 0 0 * * * hi. set the higher order 1bit page of dd ram to the page address register page address set lower order 4bits 0 1 0 1 1 0 0 lower order page address set the lower order 4 bit page of dd ram to the page address register (d) column address set high order 4bits 0 1 0 0 0 0 1 high order column add . set the higher order 4 bits column address to the reg. column address set lower order 4bits 0 1 0 0 0 0 0 lower order column add. set the lower order 4 bits column address to the reg. (e) status read 0 0 1 status 0 0 0 0 read out the internal status (f) write display data 1 1 0 write data write the data into the display data ram (g) read display data 1 0 1 read data read the data from the display data ram (h) normal or inverse on/off set 0 1 0 1 0 1 0 0 1 1 0/1 inverse the on and off display 0:normal 1:inverse (i) static drive on /normal display 0 1 0 1 0 1 0 0 1 0 0/1 whole display turns on 0:normal 1:whole disp. on (j) sub instruction table mode 0 1 0 0 1 1 1 0 0 0 0 set the sub instruction table. (k)partial display 1st block, set start display unit 0 1 0 0 0 0 0 start display unit set the start display unit of 1st block. 1st block, set the number of display units 0 1 0 0 0 0 1 number of display units set the number of display units of 1st block. 2nd block, set start display unit 0 1 0 0 0 1 0 start display unit set the start display unit of 2nd block. 2nd block, set the number of display units 0 1 0 0 0 1 1 number of display units set the number of display units of 2nd block. partial display on 0 1 0 0 1 0 0 0 0 0 0 it comes off the mode to set and a display is executed. (l)n-line inverse drive set register set higher order 2 bits 0 1 0 0 1 0 1 * * higher order set the number of inverse drive line. register set lower order 4 bits 0 1 0 0 1 1 0 lower order set the number of inverse drive line. n-line inverse drive set is executed. 0 1 0 0 1 1 1 0 0 0 0 the execution of the line inverse drive. (m)evr register set evr register set higher order 4 bits 0 1 0 1 0 0 0 evr data higher order set the v 5 output level to the evr register. (higher order 4 bits) evr register set lower order 4 bits 0 1 0 1 0 0 1 evr data lower order set the v 5 output level to the evr register. (lower order 4 bits) evr register set is executed. 0 1 0 1 0 1 0 0 0 0 0 the execution of the evr. (n) end of sub instruction table mode 0 1 0 0 1 1 1 0 0 0 1 it ends the setting of sub instruction table. (*:don't care) (*:don't care) (2) instruction (2) instruction table 4. instruction code table 4. instruction code sub sub inst. inst.

NJU6678V NJU6678V (a) display on/off (a) display on/off a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 1 1 1 d it executes the on/off control of the whole display without relation to the dd ram or any internal conditions. it executes the on/off control of the whole display without relation to the dd ram or any internal conditions. (2-1) explanation of instruction code (2-1) explanation of instruction code d 0:display off d 0:display off 1:display on 1:display on (b) display start line (b) display start line it sets the dd ram line address corresponding to the com0 terminal (normally assigned to the top display line). it sets the dd ram line address corresponding to the com0 terminal (normally assigned to the top display line). in this instruction execution, the display area is automatically set by the lines that correspond to the display duty in this instruction execution, the display area is automatically set by the lines that correspond to the display duty ratio to the upward direction of the line address. changing the line address by this instruction performs smooth ratio to the upward direction of the line address. changing the line address by this instruction performs smooth scrolling to a vertical direction. in this time, the dd ram data are unchanged. scrolling to a vertical direction. in this time, the dd ram data are unchanged. a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 line address(hex) 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 01 : : : : 1 0 0 1 1 1 1 1 9f (c) page address set (c) page address set when mpu access to the dd ram, a page address is set by page address set instruction before writing the when mpu access to the dd ram, a page address is set by page address set instruction before writing the data. (note: the change of page address is not affected to the display.) data. (note: the change of page address is not affected to the display.) a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 0 * * * a 4 a 4 a 3 a 2 a 1 a 0 page 0 0 0 0 0 0 0 0 0 0 1 1 : : : : 1 0 0 1 1 19 a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 1 a 7 a 6 a 5 a 4 0 1 0 0 1 1 0 a 3 a 2 a 1 a 0 0 1 0 1 1 0 0 a 3 a 2 a 1 a 0 (*:don't care) (*:don't care)
NJU6678V NJU6678V a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 column address(hex) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : 1 0 0 0 0 0 1 1 83 (d) column address (d) column address a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 1 a 7 a 6 a 5 a 4 when mpu accesses to the dd ram , the row address set by page address set instruction is required with the when mpu accesses to the dd ram , the row address set by page address set instruction is required with the column address before writing the data. the column address set requires twice address set which are higher column address before writing the data. the column address set requires twice address set which are higher order 4 bits address set and lower order 4 bits. order 4 bits address set and lower order 4 bits. when the mpu access to the dd ram continuously, the column address increments automatically from the set when the mpu access to the dd ram continuously, the column address increments automatically from the set address after each data access. therefore, the mpu can transmit only the data continuously without setting the address after each data access. therefore, the mpu can transmit only the data continuously without setting the column address at every transmission time. the increment of column address is stopped at the maximum column column address at every transmission time. the increment of column address is stopped at the maximum column address plus 1 limited by each display mode. when the column address count up is stopped, the row address is address plus 1 limited by each display mode. when the column address count up is stopped, the row address is not changed. not changed. 0 1 0 0 0 0 0 a 3 a 2 a 1 a 0 higher order higher order lower order lower order (e) status read (e) status read this instruction reads out the internal status of "busy", ?adc", "on/off" and "reset" described as follows. this instruction reads out the internal status of "busy", ?adc", "on/off" and "reset" described as follows. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 busy adc on/off reset 0 0 0 0 busy busy : busy=1 indicate the operating or the reset cycle. : busy=1 indicate the operating or the reset cycle. all instructions can be input after the busy status change to "0". all instructions can be input after the busy status change to "0". adc adc : indicate the output correspondence of column (segment) address and segment driver. : indicate the output correspondence of column (segment) address and segment driver. 0 :counterclockwise output (inverse) 0 :counterclockwise output (inverse) 1 :clockwise output (normal) 1 :clockwise output (normal) (note) the data "0=inverse" and "1=normal" of adc status is inverted with the adc select (note) the data "0=inverse" and "1=normal" of adc status is inverted with the adc select instruction of "1=inverse" and "0=normal". instruction of "1=inverse" and "0=normal". on/off : indicate the whole display on/off status. on/off : indicate the whole display on/off status. 0 : whole display "on 0 : whole display "on 1 : whole display "off" 1 : whole display "off" (note) the data "0=on" and "1=off" of display on/off status is inverted with the display on/off (note) the data "0=on" and "1=off" of display on/off status is inverted with the display on/off instruction data of "1=on" and "0=off". instruction data of "1=on" and "0=off". reset : indicate the initializing by res terminal signal or reset instruction. reset : indicate the initializing by res terminal signal or reset instruction. 0 : not reset status 0 : not reset status 1 : in the reset status 1 : in the reset status
NJU6678V NJU6678V (f) write display data (f) write display data a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 1 0 write data it writes the data on the data bus into the dd ram. column address increments automatically after data writing, it writes the data on the data bus into the dd ram. column address increments automatically after data writing, therefore, the mpu can write the data into the dd ram continuously without the address setting at every writing therefore, the mpu can write the data into the dd ram continuously without the address setting at every writing time once the starting address is set. time once the starting address is set. (g) read display data (g) read display data a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 0 1 read data this instruction reads out the 8-bit data from dd ram addressed by the column and the page address. the this instruction reads out the 8-bit data from dd ram addressed by the column and the page address. the column address automatically increments after the 8-bit data read out, therefore, the mpu can read the data from column address automatically increments after the 8-bit data read out, therefore, the mpu can read the data from the dd ram continuously without the address setting at every reading time once the starting address is set. the dd ram continuously without the address setting at every reading time once the starting address is set. note that the dummy read is required just after setting the column address (see ?(4-4) access to the dd ram note that the dummy read is required just after setting the column address (see ?(4-4) access to the dd ram and the internal register?). and the internal register?). in the serial interface mode, the display data is unable to read out. in the serial interface mode, the display data is unable to read out. (h) normal or inverse on/off set (h) normal or inverse on/off set a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 1 1 d it changes the display condition of normal or reverse for entire display area. the execution of this instruction does it changes the display condition of normal or reverse for entire display area. the execution of this instruction does not change the display data in the dd ram. not change the display data in the dd ram. d 0 : normal d 0 : normal ram data "1" correspond to "on" ram data "1" correspond to "on" 1 : inverse 1 : inverse ram data "0" correspond to "on" ram data "0" correspond to "on" (i) (i) static drive static drive d 0 : normal display d 0 : normal display 1 : whole display turns on 1 : whole display turns on a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 1 0 d when the ?static drive on? instruction is executed at display off status, the when the ?static drive on? instruction is executed at display off status, the NJU6678V NJU6678V operates operates in power save mode. (refer ? power save mode ?) in power save mode. (refer ? power save mode ?) this instruction turns all the pixels on regardless the data stored in the dd ram. in this time, the data in dd this instruction turns all the pixels on regardless the data stored in the dd ram. in this time, the data in dd ram are remained and unchanged. this instruction is executed prior to the "normal or inverse on/off set" ram are remained and unchanged. this instruction is executed prior to the "normal or inverse on/off set" instruction. instruction.
NJU6678V NJU6678V (j) sub instruction table mode (j) sub instruction table mode this instruction switches the instruction table from the main to the sub. the sub instruction table contains instruc- this instruction switches the instruction table from the main to the sub. the sub instruction table contains instruc- tions of partial display, n-line inverse drive set and evr register set as mentioned in (k), (l) and (m). tions of partial display, n-line inverse drive set and evr register set as mentioned in (k), (l) and (m). the instruction of sub instruction table mode must be executed before above 3 sub instructions execution. the the instruction of sub instruction table mode must be executed before above 3 sub instructions execution. the instruction of end of sub instruction table mode (n) switches the instruction table from the sub to the main. if any instruction of end of sub instruction table mode (n) switches the instruction table from the sub to the main. if any main instructions are written in the sub instruction mode, the main instructions are written in the sub instruction mode, the NJU6678V NJU6678V will malfunction. will malfunction. sub instruction table mode set sub instructions. end of sub instruction table mode. -set sub instruction table flow is shown below: -set sub instruction table flow is shown below: switches to sub instruction table mode. switches to sub instruction table mode. switches to main instruction mode. switches to main instruction mode. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 0 0 0 u n i t 1 u n i t 4 u n i t 2 u n i t 5 u n i t 3 u n i t 6 u n i t 8 u n i t 7 u n i t 9 u n i t 1 1 u n i t 1 0 u n i t 1 2 u n i t 0 ( 8 c o m m o n s ) ( 8 c o m m o n s ) (k) partial display (k) partial display display unit structure display unit structure 104-common 104-common 132-segment 132-segment it selects two active display areas on the lcd panel partially. the display area is divided to 13 units with four it selects two active display areas on the lcd panel partially. the display area is divided to 13 units with four commons each and selected two display blocks by setting unit number and number of unit required (not overlap, commons each and selected two display blocks by setting unit number and number of unit required (not overlap, not over than 13 units) to display on the lcd panel. these two display blocks are assigned optionally on the lcd not over than 13 units) to display on the lcd panel. these two display blocks are assigned optionally on the lcd panel. duty selects an adapted ratio number corresponding to the total number of two display blocks automati- panel. duty selects an adapted ratio number corresponding to the total number of two display blocks automati- cally. cally. partial display function adjusts the lcd driving voltage, voltage boosting times and e.v.r level by the instruction partial display function adjusts the lcd driving voltage, voltage boosting times and e.v.r level by the instruction to generate the optimum lcd driving voltage for display quality. as result, the operating current is reduced. to generate the optimum lcd driving voltage for display quality. as result, the operating current is reduced.
NJU6678V NJU6678V a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 0 d d d d partial display instruction partial display instruction 0 1 0 0 0 0 1 d d d d 0 1 0 0 0 1 0 d d d d start unit start unit the display unit the display unit number number start unit start unit the display unit the display unit number number 0 1 0 0 0 1 1 d d d d d :unit number (hex.) d :unit number (hex.) attention followings due to prevent from mulfunction attention followings due to prevent from mulfunction the input order of partial display instructions must follow above. the input order of partial display instructions must follow above. prohibits the overlap of the 1 prohibits the overlap of the 1 st st partial display block and the 2 partial display block and the 2 nd nd . . the start unit of the 1 the start unit of the 1 st st partial display block must not be over 12. partial display block must not be over 12. the total display unit number (the sum of the 1 the total display unit number (the sum of the 1 st st and 2 and 2 nd nd partial display block unit num partial display block unit num ber) must not be over 13. ber) must not be over 13. on the lcd panel, no active display area inserts between the 1 on the lcd panel, no active display area inserts between the 1 st st display block and the 2 display block and the 2 nd nd . . however, the display data of the 1 however, the display data of the 1 st st display block and the 2 display block and the 2 nd nd must store continuously in must store continuously in the display data ram. the display data ram. 1 1 st st block block 2 2 nd nd block block partial display partial display on on 0 1 0 0 1 0 0 0 0 0 0 notes) notes) by input following instruction, the duty ratio is changed automatically and executes by input following instruction, the duty ratio is changed automatically and executes the partial display function. the partial display function. when partial display functions, both of top unit number of display area (the start unit) and the number of the when partial display functions, both of top unit number of display area (the start unit) and the number of the effective continuous unit (display unit) from the start unit for the first display block and the second. attention that effective continuous unit (display unit) from the start unit for the first display block and the second. attention that the first display block and the second definition must not be overlap of display area and not be over than 13 units the first display block and the second definition must not be overlap of display area and not be over than 13 units in total. in total. in case of whole display (1/104 duty), the first display block defines start unit=0 (0,0,0,0) and display unit = 13 in case of whole display (1/104 duty), the first display block defines start unit=0 (0,0,0,0) and display unit = 13 (1,1,0,1) for all of display area selection. in this time, the definition of the second display block is ignored. (1,1,0,1) for all of display area selection. in this time, the definition of the second display block is ignored. in case of only the first block display, the second display block defines start unit=0 (0,0,0,0) and display unit = 0 in case of only the first block display, the second display block defines start unit=0 (0,0,0,0) and display unit = 0 (0,0,0,0) for no display area. (0,0,0,0) for no display area.
NJU6678V NJU6678V example of the partial display setting. example of the partial display setting. active display-block active display-block the above partial display condition is set as follows: the above partial display condition is set as follows: 1)set sub instruction mode 1)set sub instruction mode 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 1 0 1 a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 3)end sub instruction mode 3)end sub instruction mode duty is changed automatically when partial display execution. but lcd driving voltage, bias, driving form like as duty is changed automatically when partial display execution. but lcd driving voltage, bias, driving form like as 2-frame alternating driving or n-line inverse are not changed. therefore, display off should operate before partial 2-frame alternating driving or n-line inverse are not changed. therefore, display off should operate before partial display execution for prevention of unexpected display, and voltage booster select instruction, e.v.r register display execution for prevention of unexpected display, and voltage booster select instruction, e.v.r register set, bias select and n-line inverse driving set should set optimum conditions for good display in the mean time of set, bias select and n-line inverse driving set should set optimum conditions for good display in the mean time of partial display instruction execution. the optimum conditions should fix refering the result of actual display partial display instruction execution. the optimum conditions should fix refering the result of actual display eveluation. eveluation. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 0 0 0 set sub instruction set sub instruction mode. mode. 2)set partial display conditions 2)set partial display conditions a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 0 0 1 end sub instruction end sub instruction mode. back to main mode. back to main instruction mode. instruction mode. unit 2 unit 2 unit 3 unit 3 unit 9 unit 9 unit 10 unit 10 unit 11 unit 11 unit 12 unit 12 unit 0 unit 0 unit 1 unit 1 unit 4 unit 4 unit 8 unit 8 unit 7 unit 7 unit 5 unit 5 unit 6 unit 6 1 1 st st block block 2 2 nd nd block block 1 1 st st block, block, set start unit set start unit to ?0? to ?0? 1 1 st st block, block, set the display set the display unit number to ?2? unit number to ?2? 2 2 nd nd block, block, set start unit set start unit to ?4? to ?4? 2 2 nd nd block, block, set the display set the display units number to ?5? units number to ?5? execute partial display. execute partial display. the duty is changed to 1/56 automatically. the duty is changed to 1/56 automatically.
NJU6678V NJU6678V internal power supply off sub instruction table mode set a start unit of the first display unit set a number of display unit of the first set a start unit of the second display unit set a number of display unit of the second executes partial display function n-line inverse drive set evr register set end sub instruction table mode bias select voltage booster times select wait time internal power supply on -set partial display flow is shown below: -set partial display flow is shown below: n-line inverse register set (refer +functional description fig.3 n-line inverse alternative drive mode) n-line inverse register set (refer +functional description fig.3 n-line inverse alternative drive mode) it sets a line number to inverse the polarity of common driver and segment. it sets a line number to inverse the polarity of common driver and segment. the instructions must be input in order of followings. these instructions are sub instruction sets and must be set the instructions must be input in order of followings. these instructions are sub instruction sets and must be set after (j)sub instruction table mode. after (j)sub instruction table mode. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 1 * * a 5 a 4 0 1 0 0 1 1 0 a 3 a 2 a 1 a 0 higher order higher order low order low order a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 0 0 0 3)execute the 3)execute the n-line inverse n-line inverse (l) n-line inverse drive mode (l) n-line inverse drive mode ( ( *:2-frame alternating *:2-frame alternating drive mode.) drive mode.) a 5 a 4 a 3 a 2 a 1 a 0 inverse line 0 0 0 0 0 0 -(*) 0 0 0 0 0 1 2 : : 1 1 1 1 1 1 64 a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 0 0 0 set sub instruction set sub instruction mode. mode. 1)set sub instruction mode 1)set sub instruction mode 2)set n-line inverse number 2)set n-line inverse number 4)end sub instruction mode 4)end sub instruction mode a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 0 0 1 end sub instruction end sub instruction mode. back to main mode. back to main instruction mode. instruction mode.
NJU6678V NJU6678V it controls the voltage regulator circuit of the internal lcd power supply to adjust the lcd display contrast by it controls the voltage regulator circuit of the internal lcd power supply to adjust the lcd display contrast by changing the lcd driving voltage ?v5?. by data setting into the evr register, the lcd driving voltage ?v5? selects changing the lcd driving voltage ?v5?. by data setting into the evr register, the lcd driving voltage ?v5? selects out of 201 steps of regulated voltage. the voltage adjustable range of ?v5? is fixed by the external resistors. for out of 201 steps of regulated voltage. the voltage adjustable range of ?v5? is fixed by the external resistors. for details, refer the section ?(3-2) voltage adjust circuits?. details, refer the section ?(3-2) voltage adjust circuits?. a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 v lcd 0 0 1 1 0 1 1 1 low : : : : 1 1 1 1 1 1 1 1 high v v lcd lcd =v =v dd dd -v -v 5 5 when evr doesn't use, set the evr register to (1,1,1,1,1,1,1,1). when evr doesn't use, set the evr register to (1,1,1,1,1,1,1,1). a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 0 0 a 7 a 6 a 5 a 4 0 1 0 1 0 0 1 a 3 a 2 a 1 a 0 a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 0 0 0 3)execute the 3)execute the evr evr (m) evr register set (m) evr register set (n) end of sub instruction table mode (n) end of sub instruction table mode "end of sub instruction table mode" instruction switches instruction table from sub to main. "end of sub instruction table mode" instruction switches instruction table from sub to main. (k)partial display, (l)n-line inverse drive mode, and (m)evr are sub instruction sets on the sub instruction table. (k)partial display, (l)n-line inverse drive mode, and (m)evr are sub instruction sets on the sub instruction table. the instruction of ?end of sub instruction mode? must be set after these sub instruction sets. the the instruction of ?end of sub instruction mode? must be set after these sub instruction sets. the NJU6678V NJU6678V may occur incorrect operation if any main instructions on the main instruction table are input in mode of sub may occur incorrect operation if any main instructions on the main instruction table are input in mode of sub instruction table. instruction table. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 0 0 0 set sub instruction set sub instruction mode. mode. 1)set sub instruction mode 1)set sub instruction mode 4)end sub instruction mode 4)end sub instruction mode a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 0 0 1 end sub instruction end sub instruction mode. back to main mode. back to main instruction mode. instruction mode. 2)set evr register 2)set evr register a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 0 0 1
NJU6678V NJU6678V (o) bias select (o) bias select a 2 a 1 a 0 bias 0 0 0 1/4 0 0 1 1/5 0 1 0 1/6 0 1 1 1/7 1 0 0 1/8 1 0 1 1/9 1 1 0 1/10 1 1 1 1/11 this instruction sets the bias voltage. this instruction sets the bias voltage. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 1 * a 2 a 1 a 0 (p) boost level select (p) boost level select command booster multiple a 1 a 0 5times external capacitors connections 4times external capacitors connections 3times external capacitors connections 2times external capacitors connections 0 0 2-time 0 1 3-time 2-time 1 0 4-time 3-time 2-time 1 1 5-time 4-time 3-time 2-time a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 1 0 0 a 1 a 0 this instruction sets the boost level (2 to 5 times). when ?partial display instruction? execution, the ?boost level this instruction sets the boost level (2 to 5 times). when ?partial display instruction? execution, the ?boost level select? also must be executed. if the external capasitors are connected as the lower than 5 times boost level, select? also must be executed. if the external capasitors are connected as the lower than 5 times boost level, don?t set the boost level by the instruction over than the boost level by conecting capasitors. if set the boost level don?t set the boost level by the instruction over than the boost level by conecting capasitors. if set the boost level over than it, the device will make malfunction. over than it, the device will make malfunction. (*:don't care) (*:don't care)
NJU6678V NJU6678V (q) read modify write/end (q) read modify write/end this instruction sets the read modify write controlling the page address increment. in this mode, the column this instruction sets the read modify write controlling the page address increment. in this mode, the column address only increments when execute the display data ?write? instruction; but no change when the display data address only increments when execute the display data ?write? instruction; but no change when the display data ?read? instruction. this status is continued until the end instruction execution. when the end instruction is ?read? instruction. this status is continued until the end instruction execution. when the end instruction is executed, the column adddress goes back to the start address before the execution of this ?read modify write? executed, the column adddress goes back to the start address before the execution of this ?read modify write? instruction. this function reduces the load of mpu for repeating display data change of the fixed area (ex. cursor instruction. this function reduces the load of mpu for repeating display data change of the fixed area (ex. cursor blink). blink). a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 1 1 0 0 0 0 d note) note) in this ?read modify write? mode, out of display dara ?read?/?write?, any instructions except in this ?read modify write? mode, out of display dara ?read?/?write?, any instructions except ?column address set? can be executed. ?column address set? can be executed. - - the example of read modify write sequence the example of read modify write sequence d 0 : read modify write on d 0 : read modify write on 1 : end 1 : end page address set set to the start address of cursor display column address set read modify write start the read modify write dummy read the data is ignored column counter doesn't increase data read column counter doesn't increase data inverse by mpu data write column counter increase dummy read column counter doesn't increase data read column counter doesn't increase data write column counter increase dummy read column counter doesn't increase data read column counter doesn't increase data write column counter increase end end the read modify write no finish? yes
NJU6678V NJU6678V (r) reset (r) reset this instruction executes the following initialization. this instruction executes the following initialization. the reset by the reset signal input to the res terminal (hardware reset) is required when power turns on. this the reset by the reset signal input to the res terminal (hardware reset) is required when power turns on. this reset instruction does not use instead of this hardware reset when power turns on. reset instruction does not use instead of this hardware reset when power turns on. initialization initialization 1 1 set the column address counter to 00 set the column address counter to 00 h h 2 2 set the display start line register to 00 set the display start line register to 00 h h 3 3 set the page address register to page ?0? set the page address register to page ?0? 4 4 set the evr register to ff set the evr register to ff h h 5 5 set the partial display(1/104 duty) set the partial display(1/104 duty) 6 6 set the bias select(1/11 bias) set the bias select(1/11 bias) 7 7 set the voltage booster(5 times) set the voltage booster(5 times) 8 8 set the n-line inverse register to 0 set the n-line inverse register to 0 h h the dd ram is not affected by this initialization. the dd ram is not affected by this initialization. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 1 1 0 0 0 1 0 (s) internal power supply on/off (s) internal power supply on/off this instruction control on and off for the internal voltage converter, voltage regulator and voltage follower this instruction control on and off for the internal voltage converter, voltage regulator and voltage follower circuits. for the booster circuits operation, the oscillation circuits must be in operation circuits. for the booster circuits operation, the oscillation circuits must be in operation . . d 0 : internal power supply off d 0 : internal power supply off 1 : internal power supply on 1 : internal power supply on a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 0 0 0 0 d the internal power supply must be off when external power supply using. the internal power supply must be off when external power supply using. *1 the set up period of internal power supply on depends on the *1 the set up period of internal power supply on depends on the step up step up capacitors, voltage stabilizer capacitors, voltage stabilizer capacitors, v capacitors, v dd dd and v and v lcd lcd . . therefore it requires the actual evaluation using the lcd module to get the correct time. (refer to the therefore it requires the actual evaluation using the lcd module to get the correct time. (refer to the (3-4) fig.5) (3-4) fig.5)
NJU6678V NJU6678V (t) driver outputs on/off (t) driver outputs on/off this instruction controlls on/off of the lcd driver outputs. this instruction controlls on/off of the lcd driver outputs. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 0 0 0 1 d the the NJU6678V NJU6678V implements low power lcd driving voltage generator circuit and requires the following power implements low power lcd driving voltage generator circuit and requires the following power supply on/off sequence. supply on/off sequence. - lcd driving power supply on/off sequences - lcd driving power supply on/off sequences the sequences below are required when the power supply turns on/off. the sequences below are required when the power supply turns on/off. for the power supply turning on operation after the power-save mode, refer the ?power save release sequence? for the power supply turning on operation after the power-save mode, refer the ?power save release sequence? mentioned after. mentioned after. *1 the internal power supply rise time is depending on the condition of the supply voltage, vlcd=vdd-v5, *1 the internal power supply rise time is depending on the condition of the supply voltage, vlcd=vdd-v5, external capacitor of booster, and external capacitor connected to v external capacitor of booster, and external capacitor connected to v 1 1 to v to v 5 5 . to know the rise time correctly, . to know the rise time correctly, test by using the actual lcd module. test by using the actual lcd module. d 0 : lcd driving waveform output off d 0 : lcd driving waveform output off 1 : lcd driving waveform output on 1 : lcd driving waveform output on turn on sequence turn on sequence evr register set internal power supply on or external power supply on (wait time) *1 drivier outputs on display off whole display on internal power supply off or external power supply off driver outputs off NJU6678V power off turn off sequence turn off sequence
NJU6678V NJU6678V (u) power save (complex comand) (u) power save (complex comand) when static drive on at the display off status (inverse order also same), the internal circuits goes to the power when static drive on at the display off status (inverse order also same), the internal circuits goes to the power save mode and the operating current is dramatically reduced, almost same as the standby current. save mode and the operating current is dramatically reduced, almost same as the standby current. the internal status in the power save mode is shown as follows; the internal status in the power save mode is shown as follows; 1: the oscillation circuits and the internal power supply circuits stop the operation. 1: the oscillation circuits and the internal power supply circuits stop the operation. 2: lcd driving is stopped. segment and common drivers output v 2: lcd driving is stopped. segment and common drivers output v dd dd level voltage. level voltage. 3: the display data and the internal operating condition are remained and kept as just before enter the 3: the display data and the internal operating condition are remained and kept as just before enter the power save mode. power save mode. 4: all the lcd driving bias voltage (v1 to v5) is fixed to the v 4: all the lcd driving bias voltage (v1 to v5) is fixed to the v dd dd level. level. the power save and its release perform according to the following sequences. the power save and its release perform according to the following sequences. display off static drive on driver outputs off normal display display on (wait time) driver outputs on *1 in the power save sequence, the power save mode starts after the static drive on command is executed. *1 in the power save sequence, the power save mode starts after the static drive on command is executed. *2 in the power save release sequence, the power save mode releases just after the static drive off instruction *2 in the power save release sequence, the power save mode releases just after the static drive off instruction execution. the display on instruction is allowed to execute at any time after the static drive off instruction execution. the display on instruction is allowed to execute at any time after the static drive off instruction is completed. is completed. *3 the internal power supply rise time is depending on the condition of the supply voltage, v *3 the internal power supply rise time is depending on the condition of the supply voltage, v lcd lcd =v =v dd dd -v5, -v5, external capacitor of booster, and external capacitor connected to v external capacitor of booster, and external capacitor connected to v 1 1 to v to v 5 5 . to know the rise time cor . to know the rise time cor rectly, test by using the actual lcd module. rectly, test by using the actual lcd module. *4 lcd driving waveform is output after the exection of the driver outputs on instruction execution. *4 lcd driving waveform is output after the exection of the driver outputs on instruction execution. *5 in case of the external power supply operation, the external power supply should be turned off before the power *5 in case of the external power supply operation, the external power supply should be turned off before the power save mode and connected to the v save mode and connected to the v dd dd for fixing the voltage. in this time, v for fixing the voltage. in this time, v out out terminal also should be made terminal also should be made codition like as disconection or connection to v codition like as disconection or connection to v ss ss . . power save release sequence power save release sequence power save sequence power save sequence (v) adc select (v) adc select a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 0 0 d d 0 : clockwise output (normal) d 0 : clockwise output (normal) segment driver s segment driver s 0 0 to s to s 131 131 1 : counterclockwise output (inverse) segment driver s 1 : counterclockwise output (inverse) segment driver s 131 131 to s to s 0 0 this instruction determines the correspondence of column in the dd ram with the segment driver outputs. this instruction determines the correspondence of column in the dd ram with the segment driver outputs. segment driver output order is inversed when this instruction executes, therefore, the placement the segment driver output order is inversed when this instruction executes, therefore, the placement the NJU6678V NJU6678V against the lcd panel becomes easy. against the lcd panel becomes easy. (static drive on) (static drive on) the the NJU6678V NJU6678V constantly spends the current without the execution of the driver outputs off instruction. the lcd constantly spends the current without the execution of the driver outputs off instruction. the lcd drive waveform is not output until the driver outputs on instruction is executed. drive waveform is not output until the driver outputs on instruction is executed.
NJU6678V NJU6678V (3-1) 5-time voltage booster circuits (3-1) 5-time voltage booster circuits the 5-time voltage booster circuit outputs the negative voltage(v the 5-time voltage booster circuit outputs the negative voltage(v dd dd common) boosted 5 times of v common) boosted 5 times of v dd dd -v -v ss ss from the from the v v out out terminal with connecting the five capacitors between c terminal with connecting the five capacitors between c 1 1 + + and c and c 1 1 - - , c , c 2 2 + + and c and c 2 2 - - , c , c 3 3 + + and c and c 3 3 - - , c , c 4 4 + + and c and c 4 4 - - , and v , and v ss ss and v and v out out . the boosting time is selected out of 2 times to 5 by the combination of changing the external capacitors . the boosting time is selected out of 2 times to 5 by the combination of changing the external capacitors connection and ?booster level select? instruction. (refer (2-1)instruction (p)voltage boost time select) connection and ?booster level select? instruction. (refer (2-1)instruction (p)voltage boost time select) voltage booster circuits requires the clock signals from internal oscillation circuit or the external clock signal, voltage booster circuits requires the clock signals from internal oscillation circuit or the external clock signal, therefore, the internal oscillation circuits or the external clock supplier must be operating when the voltage booster is therefore, the internal oscillation circuits or the external clock supplier must be operating when the voltage booster is in operation. in operation. the boosted voltage of v the boosted voltage of v dd dd -v -v out out must be 17v or less. must be 17v or less. the boost voltage and the capacitor connection are shown below. the boost voltage and the capacitor connection are shown below. (3) internal power supply (3) internal power supply v v dd dd =+3v =+3v v v ss ss = = + + 0v 0v v v out out =-v =-v dd dd =-3v =-3v v v out out =-2v =-2v dd dd =-6v =-6v v v out out =-3v =-3v dd dd =-9v =-9v v v out out =-4v =-4v dd dd =-12v =-12v 2-time voltage 3-time voltage 4-time voltage 5-time voltage 2-time voltage 3-time voltage 4-time voltage 5-time voltage example of the external capacitor connection to the voltage booster circuits example of the external capacitor connection to the voltage booster circuits v s s c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - v o u t + + + + + v s s c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - v o u t + + + + 5-time voltage 4-time voltage 5-time voltage 4-time voltage 3-time voltage 2-time voltage 3-time voltage 2-time voltage v s s c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - v o u t + + + v s s c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - v o u t + + the boosted voltage and v the boosted voltage and v dd dd ,v ,v ss ss
NJU6678V NJU6678V (3-2)voltage adjust circuits (3-2)voltage adjust circuits the boosted voltage of v the boosted voltage of v out out outputs v5 for lcd driving through the voltage adjust circuits. the output voltage of v5 outputs v5 for lcd driving through the voltage adjust circuits. the output voltage of v5 is adjusted by ra and rb within the range of |v5| < |v is adjusted by ra and rb within the range of |v5| < |v out out |. |. the output is calculated by the following formula(1). the output is calculated by the following formula(1). v v lcd lcd = v = v dd dd -v -v 5 5 = (1+rb/ra)v = (1+rb/ra)v reg (1) reg (1) fig. 4 fig. 4 v d d v 5 v r e g r 1 r 2 r 3 r b r a v r v o u t the v the v reg reg voltage is a reference voltage generated by the built-in bleeder registance. v voltage is a reference voltage generated by the built-in bleeder registance. v reg reg is adjustable by evr is adjustable by evr functions (see section 3-3). functions (see section 3-3). for minor adjustment of v5, it is recommended that the ra and rb is composed of r2 as variable resistor and r1 for minor adjustment of v5, it is recommended that the ra and rb is composed of r2 as variable resistor and r1 and r3 as fixed resistors, constant should be connected to v and r3 as fixed resistors, constant should be connected to v dd dd terminal,vr and v5 ,as shown below. terminal,vr and v5 ,as shown below. < design example for r1, r2 and r3 /reference > < design example for r1, r2 and r3 /reference > r1+r2+r3=6m r1+r2+r3=6m w w (determind by the current between v (determind by the current between v dd dd -v5) -v5) variable voltage range by the r2. -7v to -11v (v variable voltage range by the r2. -7v to -11v (v lcd lcd =v =v dd dd -v5 : 10v to 12v) -v5 : 10v to 12v) (determind by the lcd electrical characteristics) (determind by the lcd electrical characteristics) vreg=3v vreg=3v (in case of v (in case of v dd dd =3v and evr=ffh) =3v and evr=ffh) r1,r2 and r3 are calculated by above conditions and the fomula of (1) to below; r1,r2 and r3 are calculated by above conditions and the fomula of (1) to below; r1=1.5m r1=1.5m w w r2=0.3m r2=0.3m w w r3=4.2m r3=4.2m w w note) v5 voltage is generated referencing with vreg voltage beased on the supply voltage (v note) v5 voltage is generated referencing with vreg voltage beased on the supply voltage (v dd dd and v and v ss ss ) as shown ) as shown in above figure. therefore, v in above figure. therefore, v lcd lcd (v (v dd dd -v5) is affected including the gain (rb/ra) by the fluctuation of v -v5) is affected including the gain (rb/ra) by the fluctuation of v reg reg voltage voltage based on the supply voltage. the power supply voltage should be stabilized for v5 stable operation. based on the supply voltage. the power supply voltage should be stabilized for v5 stable operation.
NJU6678V NJU6678V (3-3) contrast adjustment by the evr function (3-3) contrast adjustment by the evr function the evr selects the v the evr selects the v reg reg voltage out of the following 201 conditions by setting 8-bit data into the evr register. with voltage out of the following 201 conditions by setting 8-bit data into the evr register. with the evr function, v the evr function, v reg reg is controlled, and the lcd display contrast is adjusted. the evr controls the voltage of v is controlled, and the lcd display contrast is adjusted. the evr controls the voltage of v reg reg by instruction and changes the voltage of v5. by instruction and changes the voltage of v5. a step with evr is set like table shown below. a step with evr is set like table shown below. 37 37 h h to 4f to 4f h h available for use. if keeping 3% precision, sets evr over 4f available for use. if keeping 3% precision, sets evr over 4f h h . . evr register v reg [v] v lcd 3f h (0,0,1,1,0,1,1,1) (100/300) x (v dd -v ss ) low : : : : : : : : : 4f h (0,1,0,0,1,1,1,1) (124/300) x (v dd -v ss ) : : : : : : fd h (1,1,1,1,1,1,0,1) (298/300) x (v dd -v ss ) fe h (1,1,1,1,1,1,1,0) (299/300) x (v dd -v ss ) ff h (1,1,1,1,1,1,1,1) (300/300) x (v dd -v ss ) high min.4f h max.ffh adjustable range 6.2 - - - - - - - - - - - - - - - - - - - 15.0 [v] step voltagre 50 [mv] * in case of v * in case of v dd dd =3v =3v adjustable range of the lcd driving voltage by evr function adjustable range of the lcd driving voltage by evr function the adjustable range is decided by the power supply voltage v the adjustable range is decided by the power supply voltage v dd dd and the ratio of external resistors and the ratio of external resistors ra and rb. ra and rb. [ design example for the adjustable range / reference ] [ design example for the adjustable range / reference ] - condition v - condition v dd dd =3.0v, v =3.0v, v ss ss =0v =0v ra=1m ra=1m w w , rb=4m , rb=4m w w ( ra:rb=1:4 ) ( ra:rb=1:4 ) the adjustable range and the step voltage are calculated as follows in the above condition. the adjustable range and the step voltage are calculated as follows in the above condition. in case of setting 4f in case of setting 4f h h in the evr register, in the evr register, v v lcd lcd = ((ra+rb)/ra)v = ((ra+rb)/ra)v reg reg = (5/1) x [(124/300) x 3.0] = (5/1) x [(124/300) x 3.0] = 6.2v = 6.2v in case of setting ff in case of setting ff h h in the evr register, in the evr register, v v lcd lcd = ((ra+rb)/ra)v = ((ra+rb)/ra)v reg reg = (5/1) x [(300/300) x 3.0] = (5/1) x [(300/300) x 3.0] = 15.0v = 15.0v in use of the evr function, the voltage adjustment circuit must turn on by the power supply instruction. in use of the evr function, the voltage adjustment circuit must turn on by the power supply instruction.
NJU6678V NJU6678V (3-4) lcd driving voltage generation circuits (3-4) lcd driving voltage generation circuits the lcd driving bias voltage of v the lcd driving bias voltage of v 1 1 ,v ,v 2 2 ,v ,v 3 3 ,v ,v 4 4 are generated by dividing the v are generated by dividing the v 5 5 voltage with the internal bleeder resis- voltage with the internal bleeder resis- tance and is supplied to the lcd driving circuits after the impedence conversion by the voltage follower. tance and is supplied to the lcd driving circuits after the impedence conversion by the voltage follower. as shown in figure 5, five external capacitors are required to connect to each lcd driving voltage terminal for voltage as shown in figure 5, five external capacitors are required to connect to each lcd driving voltage terminal for voltage stabilization. the value of capacitors (c stabilization. the value of capacitors (c 5 5 to c to c 9 9 ) should be determined after the actual lcd panel display evaluation. ) should be determined after the actual lcd panel display evaluation. using the internal power supply using the external power supply using the internal power supply using the external power supply fig.5 fig.5 *1 short wiring or sealed wiring to the vr terminal is required due to the high impedance of vr terminal. *1 short wiring or sealed wiring to the vr terminal is required due to the high impedance of vr terminal. *2 following connection of v *2 following connection of v out out is required when external power supply using. is required when external power supply using. when v when v ss ss > v > v 5 5 --- v --- v out out =v =v 5 5 when v when v ss ss < v < v 5 5 --- v --- v out out =v =v ss ss v 1 v 2 v 3 v 4 v 5 v d d v r v o u t c 2 - c 2 + c 1 - c 1 + v s s c o u t r 3 r 2 r 1 c 1 c 2 v 5 + + + + + + + + c 5 c 6 c 7 c 8 c 9 c 3 c 4 + + c 3 - c 3 + c 4 - c 4 + * 1 e x t e r n a l v o l t a g e g e n e r a t o r v 1 v 2 v 3 v 4 v 5 v d d v r v o u t c 2 - c 2 + c 1 - c 1 + v s s v 5 c 3 - c 3 + c 4 - c 4 + * 2 c out to 1uf c1 to c4, c9 to 1uf c5 to c8 0.1 to 0.47uf r1 1.5m w r2 0.3m w r3 4.2m w reference set up value reference set up value v v lcd lcd =v =v dd dd -v5 = 10 to 12v -v5 = 10 to 12v NJU6678V NJU6678V NJU6678V NJU6678V
NJU6678V NJU6678V (4-1) interface type selection (4-1) interface type selection two mpu interface types are available in the two mpu interface types are available in the NJU6678V NJU6678V : by 1) 8-bit bi-directional data bus (d7 to d0), 2) serial data : by 1) 8-bit bi-directional data bus (d7 to d0), 2) serial data input (si:d7). the interface type (the 8 bit parallel or serial interface) is determined by the condition of the p/s input (si:d7). the interface type (the 8 bit parallel or serial interface) is determined by the condition of the p/s terminals connecting to ?h? or ?l? level as shown in table 5. in case of the serial interface, neither the status read-out terminals connecting to ?h? or ?l? level as shown in table 5. in case of the serial interface, neither the status read-out nor the ram data read-out operation is allowed. nor the ram data read-out operation is allowed. (4) mpu interface (4) mpu interface table 5 table 5 the the NJU6678V NJU6678V interfaces the 68- or 80-type mpu directly if the parallel interface (p/s=?h?) is selected. interfaces the 68- or 80-type mpu directly if the parallel interface (p/s=?h?) is selected. the 68-type or 80-type mpu is selected by connecting the sel68 terminal to ?h? or ?l? as shown in table 6. the 68-type or 80-type mpu is selected by connecting the sel68 terminal to ?h? or ?l? as shown in table 6. parallel interface parallel interface table 6 table 6 (4-2) discrimination of data bus signal (4-2) discrimination of data bus signal c s d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 3 6 4 1 0 2 1 7 5 8 9 s i s c l a 0 p/s type cs a0 rd wr sel68 d 7 d 6 d 0 to d 5 h parallel cs a0 rd wr sel68 d 7 d 6 d 0 to d 5 l serial cs a0 - - - si scl hi-z sel68 type cs a0 rd wr d 0 to d 7 h 68 type mpu cs a0 e r/w d 0 to d 7 l 80 type mpu cs a0 rd wr d 0 to d 7 the the NJU6678V NJU6678V discriminates the mean of signal on the data bus by the combination of a0, e, r/w, and (rd,wr) discriminates the mean of signal on the data bus by the combination of a0, e, r/w, and (rd,wr) signals as shown in table 7. signals as shown in table 7. table 7 table 7 common 68 type 80 type function a0 r/w rd wr h h l h read display data h l h l write display data l h l h status read l l h l write into the register(instruction) (4-3) serial interface.(p/s="l") (4-3) serial interface.(p/s="l") the serial interface of the the serial interface of the NJU6678V NJU6678V consists of the 8-bit shift register and 3-bit counter. in case the chip is consists of the 8-bit shift register and 3-bit counter. in case the chip is selected (cs=l), the input to d7(si) and d6(scl) becomes available, and in case that the chip isn?t selected, the selected (cs=l), the input to d7(si) and d6(scl) becomes available, and in case that the chip isn?t selected, the shift register and the counter are reset to the initial condition. shift register and the counter are reset to the initial condition. the data input from the terminal(si) is msb first like as the order of d7, d6, the data input from the terminal(si) is msb first like as the order of d7, d6, d0 by a serial interface, it is d0 by a serial interface, it is entered into with rise edge of serial clock(scl). the data converted into parallel data of 8-bit with the rise edge of entered into with rise edge of serial clock(scl). the data converted into parallel data of 8-bit with the rise edge of 8th serial clock and processed. 8th serial clock and processed. it discriminates display data or instructions by a0 input terminal. a0 is read with rise edge of (8 x n)th of serial it discriminates display data or instructions by a0 input terminal. a0 is read with rise edge of (8 x n)th of serial clock (scl), it is recognized display data by a0=h? and instruction by a0=?l?. a0 input is read in the rise edge of clock (scl), it is recognized display data by a0=h? and instruction by a0=?l?. a0 input is read in the rise edge of (8 x n)th of serial clock (scl) after chip select and distinguished. (8 x n)th of serial clock (scl) after chip select and distinguished. however,in case of res=?h? to ?l? or cs=?l? to ?h? with trasfered data does not fill 8 bit, attention is necessary however,in case of res=?h? to ?l? or cs=?l? to ?h? with trasfered data does not fill 8 bit, attention is necessary because it will processed as there was command input. always, input the data of (8 x n) style. because it will processed as there was command input. always, input the data of (8 x n) style. the scl signal must be careful of the termination reflection by the wiring length and the external noise and the scl signal must be careful of the termination reflection by the wiring length and the external noise and confirmation by the actual machine is recommended by it. confirmation by the actual machine is recommended by it. fig. 6 fig. 6
NJU6678V NJU6678V (4-4) access to the display data ram and internal register. (4-4) access to the display data ram and internal register. the the NJU6678V NJU6678V transfers data to the cpu through the bus holder with the internal data bus. transfers data to the cpu through the bus holder with the internal data bus. in case of reading out the display data contents in the dd ram, the data which was read in the first data read cycle in case of reading out the display data contents in the dd ram, the data which was read in the first data read cycle (= the dummy read ) is memorized in the bus holder. then the data is read out to the system bus from the bus holder (= the dummy read ) is memorized in the bus holder. then the data is read out to the system bus from the bus holder in the next data read cycle. also, in case that the mpu writes into dd ram, the data is temporarily stored in the bus in the next data read cycle. also, in case that the mpu writes into dd ram, the data is temporarily stored in the bus holder and is then written into dd ram by the next data write cycle. holder and is then written into dd ram by the next data write cycle. therefore, the limitation of the access to therefore, the limitation of the access to NJU6678V NJU6678V from mpu side is not access time (t from mpu side is not access time (t acc acc ,t ,t ds ds ) of display data ) of display data ram and the cycle time becomes dominant. with this, speed-up of the data transfer with the mpu becomes ram and the cycle time becomes dominant. with this, speed-up of the data transfer with the mpu becomes possible. in case of cycle time isn?t met, the mpu inserts nop operation only and becomes an equivalent to an possible. in case of cycle time isn?t met, the mpu inserts nop operation only and becomes an equivalent to an execution of wait operation on the sutisfy condition in mpu. execution of wait operation on the sutisfy condition in mpu. when setting an address, the data of the specified address isn?t output immediately by the read operation after when setting an address, the data of the specified address isn?t output immediately by the read operation after setting an address, and the data of the specified address is output at the the 2nd data read operation. therefore, the setting an address, and the data of the specified address is output at the the 2nd data read operation. therefore, the dummy read is always necessary once after the address set and the write cycle. (see fig. 7) dummy read is always necessary once after the address set and the write cycle. (see fig. 7) the exsample of read modify write operaion is mentioned in (2-1)instruction ?(q)the sequence of inverse display. the exsample of read modify write operaion is mentioned in (2-1)instruction ?(q)the sequence of inverse display. w r d a t a b u s h o l d e r w r m p u i n t e r n a l t i m i n g n n + 1 n + 2 n + 3 n n + 1 n + 2 n + 3 w r d a t a b u s h o l d e r w r m p u i n t e r n a l t i m i n g r d n n n n + 1 a d d r e s s s e t n d u m m y r e a d d a t a r e a d n d a t a r e a d n + 1 r d c o l u m n a d d r e s s n n + 1 n + 2 n n n + 1 n + 2 write operation write operation read operation read operation fig.7 fig.7 (4-6) chip select (4-6) chip select cs is the chip select terminal. in case of cs=?l?, the interface with mpu is available. cs is the chip select terminal. in case of cs=?l?, the interface with mpu is available. in case of cs=?h? (chip is not selected), the terminals of d in case of cs=?h? (chip is not selected), the terminals of d 0 0 to d to d 7 7 are high impedance and a0, rd, wr, d are high impedance and a0, rd, wr, d 7 7 (si) and (si) and d d 6 6 (scl) inputs are ignored. if the serial interface is selected when cs=?h?, the shift register and the counter for the (scl) inputs are ignored. if the serial interface is selected when cs=?h?, the shift register and the counter for the serial interface are reset. serial interface are reset. however, the reset signal is always input and executed in any conditions of cs. however, the reset signal is always input and executed in any conditions of cs.
NJU6678V NJU6678V vdd vdd vdd vdd vss vss v5 v5 p a r a m e t e r symbol r a t i n g s unit supply voltage (1) v dd -0.3 to +5.0 v supply voltage (2) v 5 v dd -17.0 to v dd +0.3 v supply voltage (3) v 1 to v 4 v 5 to v dd +0.3 v input voltage v in -0.3 to v dd +0.3 v operating temperature t opr -30 to +80 c storage temperature t stg -55 to +125 (chip) c -55 to +100 (tcp) absolute maximum ratings absolute maximum ratings (ta=25 (ta=25 c) c) note 1) all voltage values are specified as v note 1) all voltage values are specified as v ss ss =0v. =0v. note 2) the relation of v note 2) the relation of v dd dd 3 3 v1 v1 3 3 v2 v2 3 3 v3 v3 3 3 v4 v4 3 3 v5>vout;v v5>vout;v dd dd >v >v ss ss 3 3 v v out out must be maintained. must be maintained. in case of inputting external lcd driving voltage , the lcd drive voltage should start supplying to in case of inputting external lcd driving voltage , the lcd drive voltage should start supplying to NJU6678V NJU6678V at the mean time of turning on v at the mean time of turning on v dd dd power supply or after turned on v power supply or after turned on v dd dd . . in use of the voltage boost circuit, the condition that the supply voltage: 17.0v in use of the voltage boost circuit, the condition that the supply voltage: 17.0v 3 3 v v dd dd -v -v out out is necessary. is necessary. note 3) if the lsi are used on condition beyond the absolute maximum rating, the lsi may be destroyed. note 3) if the lsi are used on condition beyond the absolute maximum rating, the lsi may be destroyed. using lsi within electrical characteristics is strongly recommended for normal operation. using lsi within electrical characteristics is strongly recommended for normal operation. use beyond the erectric characteristics conditions will cause malfunction and poor reliability. use beyond the erectric characteristics conditions will cause malfunction and poor reliability. note 4) decoupling capacitor should be connected between v note 4) decoupling capacitor should be connected between v dd dd and v and v ss ss due to the stabilized operation for the due to the stabilized operation for the voltage converter. voltage converter.
NJU6678V NJU6678V p a r a m e t e symbol c o n d i t i o n s min. typ. max. unit note operating voltage(1) v dd 2.5 3.3 v 5 operatingvoltage(2) v 5 v dd -17.0 v dd -6.0 v 6 v 1 ,v 2 v lcd = v dd -v 5 vdd-0.5vlcd v dd v 3 ,v 4 v 5 vdd-0.5vlcd input voltage high level v ihc1 d 0 ...d 7 ,a0, cs,res,rd,wr,sel68, p/s terminals 0.8v dd v dd v low level v ilc1 v ss 0.2v dd v output voltage high level v ohc11 d 0 ...d 7 terminals i oh =-0.5ma 0.8v dd v dd v low level v olc11 i ol = 0.5ma v ss 0.2v dd v input leakage current i lio all input terminals - 1.0 1.0 ua driver on-resistance r on1 ta=25 c v lcd =15.0v 2.0 3.0 k w 7 r on2 v lcd =8.0v 3.0 4.5 stand-by current i ddq during power save mode 0.05 5 ua 8 operating current i dd12 display v lcd =12.0v 15 40 ua i dd21 accessing f cyc =200khz 600 800 9 input terminal capacitance c in a0,cs,res,rd,wr,sel68, p/s,t1,t2,d 0 ...d 7 ta=25 c 10 pf 10 oscillation frequency f osc ta=25 c 26 32 38 khz electrical characteristics (1) (vdd=2.5v to 3.3v, vss=0v, ta=-30 to +80 electrical characteristics (1) (vdd=2.5v to 3.3v, vss=0v, ta=-30 to +80 c c ) ) voltage booster output volt. v out1 v ss -vout, 5-time voltage booster, v dd =3v v dd -15.0v v dd -14.5v v on-resistance r tri v dd =3v;c out =1.0uf 5-time voltage booster 4000 6000 w adjustment range of lcd driving volt. v out2 voltage booster circuit "off" v dd -17.0v v dd -6.0v v 13 voltage follower v 5 voltage adjustment circuit "off" v dd -17.0v v dd -6.0v v operating current i out1 v dd =3v, v lcd =12v com/seg terminals open no access display checkered pattern 160 320 ua 14 i out2 35 70 i out3 25 50 voltage reg. v reg% v dd =3v,ta=25 c, v reg =4f to ff h 3 % reset tim e t r res terminal 1.0 us 11 reset "l" level pulse width t rw res terminal 10 us 12 note 5) although the note 5) although the NJU6678V NJU6678V can operate in wide range of the operating voltage, it shall not be guaranteed in can operate in wide range of the operating voltage, it shall not be guaranteed in a sudden voltage fluctuation during the access with mpu. a sudden voltage fluctuation during the access with mpu. note 6) the operating voltage when using external power supply. note 6) the operating voltage when using external power supply. note 7) r note 7) r on on is the resistance values in supplying 0.1v voltage-difference beteen power supply terminals is the resistance values in supplying 0.1v voltage-difference beteen power supply terminals (v1,v2,v3,v4) and each output terminals (common/ segment). this is specified within the range of (v1,v2,v3,v4) and each output terminals (common/ segment). this is specified within the range of operating voltage(2). operating voltage(2). note 8,9) the value of after driver output on instruction execution. note 8,9) the value of after driver output on instruction execution. note 8,9) refers to the current consumption of the ic itself; external power supply is used for the lcd driving. in note 8,9) refers to the current consumption of the ic itself; external power supply is used for the lcd driving. in case of not use internal power supply circuit,meaning current of ic?s. lcd driving power supply are case of not use internal power supply circuit,meaning current of ic?s. lcd driving power supply are external power supply. external power supply. note 8) applicable in case of not accessing to the mpu. note 8) applicable in case of not accessing to the mpu. note 9) the operating current when writing a vertical stripe pattern on the tcyc. current consumption during the note 9) the operating current when writing a vertical stripe pattern on the tcyc. current consumption during the access is approximately proportional to the access frequency. when not accessed, it consumpts only i access is approximately proportional to the access frequency. when not accessed, it consumpts only i dd01 dd01 note 10) apply to a0, d note 10) apply to a0, d 0 0 -d -d 7 7 , rd,wr,cs,res,sel68,p/s,t , rd,wr,cs,res,sel68,p/s,t 1 1 ,t ,t 2 2 terminals. terminals.
NJU6678V NJU6678V symbol status operating condition external voltage supply (input terminal) t 1 t 2 internal oscillator voltage booster voltage adjustment voltage follower i out1 l l/h validity validity validity validity unuse i out2 h l validity invalidity validity validity use(v out ) i out3 h h validity invalidity invalidity validity use(v out ,v 5 ) a n j u 6 6 7 8 c 1 + c 1 - c 2 + c 2 - + + + v s s v d d v r v 5 t 1 t 2 v o u t c 3 + c 3 - c 4 + c 4 - + + a n j u 6 6 7 8 c 1 + c 1 - c 2 + c 2 - v s s v d d v r v 5 t 1 t 2 v o u t c 3 + c 3 - c 4 + c 4 - a n j u 6 6 7 8 c 1 + c 1 - c 2 + c 2 - v s s v d d v r v 5 t 1 t 2 v o u t c 3 + c 3 - c 4 + c 4 - :i :i out1 out1 :i :i out2 out2 measurement block diagram measurement block diagram :i :i out3 out3 NJU6678V NJU6678V NJU6678V NJU6678V NJU6678V NJU6678V note 11) t note 11) t r r ( reset time ) refers to the reset completion time of the internal circuits from the rise edge of the res ( reset time ) refers to the reset completion time of the internal circuits from the rise edge of the res signal. signal. note 12) apply minimum pulse width of the res signal. to reset, the ?l? pulse over t note 12) apply minimum pulse width of the res signal. to reset, the ?l? pulse over t rw rw shall be input. . shall be input. . note 13) the voltage adjustment circuit controls v5 within the range of the voltage follower operating voltage. note 13) the voltage adjustment circuit controls v5 within the range of the voltage follower operating voltage. note 14) each operating current shall be defined as being measured in the following condition. note 14) each operating current shall be defined as being measured in the following condition.
NJU6678V NJU6678V bus timing characteristics bus timing characteristics - read/write operation sequence (80 type mpu) - read/write operation sequence (80 type mpu) a 0 , c s d 0 t o d 7 ( w r i t e ) w r , r d d 0 t o d 7 ( r e a d ) t c y c 8 t a w 8 t c c h t c c l t a h 8 t d s 8 t d h 8 t a c c t o h 8 t f t r (v (v dd dd = = 2.5v to 3.3v 2.5v to 3.3v ,ta= ,ta= -30 to +80 -30 to +80 c c ) ) p a r a m e t e r symbo- l min. typ. max. condition unit address hold time a0,cs terminals t ah8 10 ns address set up time t aw8 0 ns system cycle time wr wr,rd terminals tcyc8 (w) 270 220 ns rd t cyc8 (r) 350 ns control pulse width wr,"l" t ccl (w) 50 ns rd,"l" t ccl (r) 200 ns wr,"h" t cch (w) 220 160 ns rd,"h" t cch (r) 150 ns data set up time d 0 to d 7 terminals t ds8 35 ns data hold time t dh8 15 ns rd access time t acc8 120 cl=100pf ns output disable time t oh8 0 50 ns rise time, fall time cs, wr, rd, a0, d0 to d7 terminals t r ,t f 15 ns note 15) note 15) all timing based on 20% and 80% of v all timing based on 20% and 80% of v dd dd voltage level. voltage level.
NJU6678V NJU6678V - read/write operation sequence (68 type mpu) - read/write operation sequence (68 type mpu) a 0 , c s d 0 t o d 7 ( w r i t e ) r / w d 0 t o d 7 ( r e a d ) t c y c 6 t a w 6 t e w h t a h 6 t d s 6 t d h 6 t a c c 6 t o h 6 t f t r e t e w l p a r a m e t e r symbol min. typ. max. condition unit address hold time a0,cs,r/w terminals t ah6 10 ns address set up time t aw6 0 ns system cycle time(w) t cyc6 (w) 270 220 ns system cycle time(r) t cyc 6(r) 350 ns enable pulse width read"h" e terminal t ewh 200 ns write"h" 50 ns read"l" t ewl 220 160 ns write"l" 150 ns data set up time d 0 to d 7 terminals t ds6 35 ns data hold time t dh6 15 ns access time t acc6 200 cl=100pf ns output disable time t oh6 0 50 ns rise time, fall tim e a0, cs, r/w, e, d 0 to d 7 terminals t r ,t f 15 ns note 16) note 16) all timing are based on 20% and 80% of v all timing are based on 20% and 80% of v dd dd voltage level. voltage level. note 17) note 17) t t cyc6 cyc6 shows the cycle of the e signal in active cs. shows the cycle of the e signal in active cs. (v (v dd dd = = 2.5v to 3.3v 2.5v to 3.3v ,ta= ,ta= -30 to +80 -30 to +80 c c ) )
NJU6678V NJU6678V scl scl scl 8th clock scl 8th clock scl 1st clock scl 1st clock scl"l"pulse width scl"l"pulse width (between the (between the instruction and next) instruction and next) instruction n instruction n instruction n+1 instruction n+1 450 ns 450 ns - write operation sequence (serial interface) - write operation sequence (serial interface) c s s c l a 0 s i t s c y c t s a s t s h w t s a h t c s h t s l w t s d s t s d h t f t r t c s s p a r a m e t e r symbol min. typ. max. condition unit serial clock cycle scl terminal t scyc 120 ns scl "h" pulse width t shw 40 ns scl "l" pulse width t slw 80 ns address set up time a0 terminal t sas 0 ns address hold time t sah 150 ns data set up time si terminal t sds 25 ns data hold time t sdh 10 ns cs-scl time cs terminal t css 10 ns t csh 300 ns rise time, fall tim e scl, a0, cs, si terminals t r ,t f 15 ns note 18) note 18) all timing are based on 20% and 80% of v all timing are based on 20% and 80% of v dd dd voltage level. voltage level. note 19) note 19) when inputting an instruction continuously, keep 450ns as the cycle of scl between the instructions as when inputting an instruction continuously, keep 450ns as the cycle of scl between the instructions as follows follows (v (v dd dd = = 2.5v to 3.3v 2.5v to 3.3v ,ta= ,ta= -30 to +80 -30 to +80 c c ) )
NJU6678V NJU6678V lcd driving waveform lcd driving waveform v d d v 1 v 2 v 3 v 4 v 5 c o m 1 c o m 0 c o m 1 c o m 2 c o m 3 c o m 4 c o m 5 c o m 6 c o m 7 c o m 8 c o m 9 c o m 1 0 c o m 1 1 c o m 1 2 c o m 1 3 c o m 1 4 s e g 1 s e g 0 c o m 1 5 s e g 1 s e g 2 s e g 3 s e g 4 1 2 3 4 1 0 2 1 2 3 4 5 c o m 2 c o m 0 s e g 0 0 0 v d d v s s c o m 0 - s e g 0 v d d - v 1 - v 2 - v 3 - v 4 - v 5 v 5 v 4 v 3 v 2 v 1 c o m 0 - s e g 1 v d d - v 1 - v 2 - v 3 - v 4 - v 5 v 5 v 4 v 3 v 2 v 1 f r 1 0 3 1 0 2 1 0 3 v d d v 1 v 2 v 3 v 4 v 5 v d d v 1 v 2 v 3 v 4 v 5 v d d v 1 v 2 v 3 v 4 v 5 v d d v 1 v 2 v 3 v 4 v 5
NJU6678V NJU6678V application circuit application circuit mpu interface (examples) mpu interface (examples) the the NJU6678V NJU6678V is connectable to 80-type mpu or 68-type. in use of serial interface, it is possible to be controlled by is connectable to 80-type mpu or 68-type. in use of serial interface, it is possible to be controlled by the signal line with the more small being. the signal line with the more small being. *:sel68 terminal shall be connected to v *:sel68 terminal shall be connected to v dd dd or v or v ss ss . . m p u a 0 a 1 t o a 7 r e s a 0 c s r e s r e s e t s e l 6 8 p / s v c c g n d n j u 6 6 7 8 v s s v d d a 0 a 1 t o a 1 5 v m a d 0 t o d 7 e r / w r e s a 0 c s d 0 t o d 7 e r / w r e s r e s e t s e l 6 8 p / s g n d a 0 a 1 t o a 7 i o r q d 0 t o d 7 r d w r r e s a 0 c s s i s c l r e s r e s e t s e l 6 8 p / s g n d p o r t 1 p o r t 2 v d d o r g n d d 0 t o d 7 r d w r v c c v d d v s s v c c v d d v s s m p u d e c o d e r n j u 6 6 7 8 m p u d e c o d e r n j u 6 6 7 8 d e c o d e r - - 80 type mpu 80 type mpu - - 68 type mpu 68 type mpu - - serial interface serial interface NJU6678V NJU6678V NJU6678V NJU6678V NJU6678V NJU6678V
NJU6678V NJU6678V l c d p a n e l ( 1 0 4 x 1 3 2 ) n j u 6 6 7 8 c 5 2 c 1 0 3 s 0 c 0 c 5 1 s 1 3 1 b o t t o m v i e w lcd panel interface example lcd panel interface example caution caution the specifications on this databook are only the specifications on this databook are only given for information , without any guarantee given for information , without any guarantee as regards either mistakes or omissions. the as regards either mistakes or omissions. the application circuits in this databook are application circuits in this databook are described only to show representative usages described only to show representative usages of the product and not intended for the of the product and not intended for the guarantee or permission of any right including guarantee or permission of any right including the industrial rights. the industrial rights. NJU6678V NJU6678V

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